Datasheet
1 Block diagram
Debug
Core0
1000MHz
Cortex-A53
32KB
I-Cache
32KB
D-Cache
NEON/FPU
Core1
1000MHz
Cortex-A53
32KB
I-Cache
32KB
D-Cache
NEON/FPU
256KB
L2-
Cache
SCU
Core2
1000MHz
Cortex-A53
32KB
I-Cache
32KB
D-Cache
NEON/FPU
Core3
1000MHz
Cortex-A53
32KB
I-Cache
32KB
D-Cache
NEON/FPU
256KB
L2-
Cache
SCU
128-bits 128-bits
CCI-400 incl. EDC
128-bits 128-bits
SRAM - all others
64-bits AHB
Concentrator
64-bits
AHB
64-bits
AHB
32-bits
AHB
DMA
MEM
eDMA
64-bits
AHB
16KB
I-Cache
CoreP
133MHz
Cortex-
M4
64KB
TCM
16KB
D-Cache
64-bits
AHB
64-bits
AHB
BIU
CSE-FL Security
Engine
Sideband
Outputs
1KB
ROM
FUSE IF
16KB
DRAM
64-bits
Peripheral
Bridge 0
64-bits64-bits64-bits
OTFAD
ROM
Ctrl
64-bits
AHB
QuadSPI
NOR Flash Ctrl
Peripheral
Bridge 1
64-bits
SRAM -
all others
64-bits
64-bits
AHB
DRAM -
all others
64-bits
Cortex-A53
AXBS Bus System incl. EDC
XRDC
32-bits
Cores
PCIe/ENET
all others
FastDMA
APEX-2_1
APEX-2_0
DCU
GPU
H.264 Dec
NVIC
BlkDMA
32KB
IMEM
Seq
DMA
32KB
DMEM
MEMIF
CMEM
16x 2Kx64
APEX-2_1
(2xAPU)
BlkDMA
32KB
IMEM
DMA
32KB
DMEM
MEMIF
CMEM
16x 2Kx64
APEX-2_0
(2xAPU)
MC
128-
bits
MC
128-
bits
16-bit VIU
64-
bits
CDC420
Encoder
GPU
GC3000
DEC200
Decoder
Display
Control
Unit
(2D-ACE)
MC
DEC200
Encoder
CRC
Fast
DMA
128-
bits
64-
bits
64-
bits
XRDC
QoS 301 incl. EDC
XRDC
Cores
PCIe/ENET
all others
FastDMA
APEX-2_1
APEX-2_0
VIU_H264
XRDC
128-bits
XRDC
128-
bits
128-
bits
Hierarchical NIC 301 AXI Bus System incl. EDC
XRDC
4KB
PRAM
SEQ
SCU
DRAM-ECC
32-bit MMDC_0
LPDDR2
DDR3(L)
DDR-PHY
SRAM Controller
Multi Ported
Multi Banked
64KB
CRAM
16KB
KRAM
Sequencer
4MB SRAM
24+Banks
ECC x64 Internal
32-bit MMDC_1
LPDDR2
DDR3(L)
DDR-PHY
4/2x4/8-bits
QSPI Flash
External NOR Flash
Off-Chip
2x4-bits
64 KB
ROM
(boot)
32-bits
MC
CGM, RGM,
PCU, ME
STCU
PIT_0
STM_0
SWT_1
SWT_0
32-bits
SDHC
FlexRay
SIPI+LFAST
320 Mbps
10 Mbps
1 Gbps
5 Gbps
24-bit
RGB
Display IF
100MHz
100MHz
4 Lanes
4 Lanes
PCIe
Ethernet AVB
ChanMux
ChanMux
MIPI-CSI2
ISP0
MIPI-CSI2
ISP1
ISP2
ISPN
H.264 Encoder
H.264 Decoder
JPEG Decoder
• • •
OCOTP_CTRL
Wake Up
SIUL
SARADC_0
FlexTimer_0
IIC_0
Linflex_0
CAN_FD_0
DSPI_0
DSPI_2
CRC_0
FCCU
CRC_1
DSPI_3
DSPI_1
CAN_FD_1
Linflex_1
IIC_2
IIC_1
FlexTimer_1
SWT_4
SWT_3
SWT_2
STM_1
INTC_MON
CGM-CMUs
PIT_1
SSE
TSENS
PMC
ERM + EIM
MSCM
SEMA4
MEMU
32-bits
MC
MPU
Debug
Debug
Debug
Debug Debug
Debug Debug Debug Debug
16-bit VIU
Seq
GIC-400
533 MHz
1066 MT/s
DDR
533 MHz
1066 MT/s
DDR
DRAM-ECC
Figure 1. Block diagram
2
Family comparison
2.1 Feature Set
This family of devices supports the following features:
Table 1. Feature Set
Feature S32V234 S32V232
ARM Cortex-A53 Core • Up to 1000 MHz Quad ARM Cortex-A53
• 32 KB/32 KB I-/D- L1 Cache
• NEON MPE co-processor
• Dual precision FPU
• 256 KB L2 Cache per cluster
• MMU
• GIC interrupt controller
• Up to 1000 MHz Dual ARM Cortex-A53
(single cluster)
• The remaining features are same as
S32V234
Table continues on the next page...
Block diagram
S32V234 Data Sheet, Rev. 8, 01/2019
NXP Semiconductors 5