Datasheet

Differential TX
Data Lines
pad_p/pad_n
Trise
Tfall
90%
10%
V
IH
V
IL
Figure 30. Rise/fall time
6.5.3.2 LFAST Interface electrical characteristics
Table 39. LFAST electrical characteristics
Symbol Parameter Conditions Value
1
Unit
Min Typ Max
V
DDIO_LFAST
Operating supply conditions — 1.71 — 1.95 V
Data Rate
DATARATE Data rate — — 312/320 Typ+0.1% Mbps
STARTUP
T
STRT_BIAS
Bias startup time
2
— — 0.5 3 µs
TRANSMITTER
V
OS_DRF
Common mode voltage — 1.1 1.2 1.475 V
|Δ
VOD_DRF
| Differential output voltage
swing (terminated)
— 250 350 450 mV
T
TR_DRF
Rise/Fall time (20% - 80% of
swing)
3
— 0.1 — 0.73 ns
C
OUT_DRF
Capacitance
4
— — — 5 pF
RECEIVER
V
ICOM_DRF
Common mode voltage — 0.15
5
— 1.5
6
V
|Δ
VI_DRF
| Differential input voltage — 150 — — mV
R
IN_DRF
Terminating resistance — 80 100 150 Ω
C
IN_DRF
Capacitance
7
— — 3.5 6 pF
L
IN_DRF
Parasitic Inductance
8
— — 5 10 nH
LFAST Clock characteristics
F
RF_REF
SysClk Frequency — 10 — 26 MHz
ERR
REF
SysClk Frequency Error — -1 — 1 %
DC
REF
SysClk Duty Cycle — 45 — 55 %
1. All values need to be confirmed during device characterization.
2. Startup time is defined as the time taken by LFAST current reference block for settling bias current after its pwr_down
(power down) has been deasserted. LFAST functionality is guaranteed only after the startup time.
3. Rise/fall time is defined for 20 to 80% signal voltage levels, at 2pF Cload and 100 Ohm termination resistor load.
4. Total lumped capacitance including silicon, package pin and bond wire. Application board simulation needed to verify
LFAST template compliancy.
5. Absolute min = 0.15 V - (250 mV/2) = 0.025 V
6. Absolute max = 1.5 V + (450 mV/2) = 1.725 V
LFAST electrical characteristics
S32V234 Data Sheet, Rev. 8, 01/2019
NXP Semiconductors 49