Datasheet

Table 38. DDR mode timing specification
ID Parameter Symbols Min Max Unit
Card Input Clock
DD1 Clock Frequency
(eMMC4.4 DDR)
f
PP
0 52 MHz
DD1 Clock Frequency (SD3.0
DDR)
f
PP
0 50 MHz
DD2 Clock Duty Cycle t
DC
45 55 %
uSDHC Output/Card Inputs CMD, DAT (Reference to CLK)
DD3 CLK to Data Valid t
DVO
— 6.2 ns
DD4 CLK to Data Invalid t
HO
2.5 — ns
DD5 CLK to CMD Valid t
DVO
— 3.25 ns
DD6 CLK to CMD Invalid t
HO
–6.2 — ns
uSDHC Input/Card Outputs CMD, DAT (Reference to CLK)
DD7 Data Input Setup Time t
SUI
2.3 — ns
DD8 Data Input Hold Time t
HI
1.5 — ns
DD9 CMD Input Setup Time t
SUI
4.5 — ns
DD10 CMD Input Hold Time t
HI
0 — ns
Communication modules
S32V234 Data Sheet, Rev. 8, 01/2019
NXP Semiconductors 47