Datasheet

Table 37. SDR mode timing specification (continued)
ID Parameter Symbols Min Max Unit
SD3 CLK to Data/CMD Valid t
DVO
— 3.2 ns
SD4 CLK to Data/CMD Invalid t
HO
-6.3 — ns
eSDHC Input/Card Outputs CMD, DAT (Reference to CLK)
SD5 DATA/CMD Input Setup
time
t
SUI
4.5 — ns
SD6 DATA/CMD Input Hold
time
t
HI
0 — ns
1. In low speed mode, card clock must be lower than 400 kHz, voltage ranges from 2.7 to 3.6 V.
2. In normal (full) speed mode for SD/SDIO card, clock frequency can be any value between 0–25 MHz. In high-speed mode,
clock frequency can be any value between 0–50 MHz.
3. In normal (full) speed mode for MMC card, clock frequency can be any value between 0–20 MHz. In high-speed mode,
clock frequency can be any value between 0–52 MHz.
6.5.2.2 DDR mode timing specifications
Figure 25. DDR Data Read timing
Communication modules
S32V234 Data Sheet, Rev. 8, 01/2019
NXP Semiconductors 45