Datasheet

PCSx
10
9
12
11
SCK Output
SCK Output
SIN
SOUT
First Data
Data
Last Data
First Data
Data
Last Data
(CPOL=0)
(CPOL=1)
Figure 21. DSPI modified transfer format timing — master, CPHA = 1
PCSx
7
8
PCSS
Figure 22. DSPI PCS strobe (PCSS) timing
6.5.2
Ultra High Speed SD/SDIO/MMC Host Interface (uSDHC)
Booting from eMMC must be at voltage of 3.3 V. The operation at 1.8 V is possible only
during run-time, that is after the boot has completed. This voltage restriction during
booting does not apply to SD/SDIO/SDHC/SDXC modes.
Measurements are with a load of 40 pF on output pins. Input slew = 1 ns,
SIUL2_MSCRn[DSE] = 101, and SIUL2_MSCRn[SRE] = 11.
uSDHC_VEND_SPEC[CMD_OE_PRE_EN] field should be programmed to 1 for proper
functioning of uSDHC external interface.
NOTE
These are not necessarily the default configuration after chip
resets. You must ensure the above chip configuration to match
the measurements in this section.
Communication modules
S32V234 Data Sheet, Rev. 8, 01/2019
NXP Semiconductors 43