Datasheet

5
6
9
12
11
10
Last Data
Last Data
SIN
SOUT
SS
First Data
First Data
Data
Data
SCK Input
SCK Input
(CPOL=0)
(CPOL=1)
Figure 19. DSPI classic SPI timing — slave, CPHA = 1
PCSx
3
1
4
10
4
9
12
11
SCK Output
SCK Output
SIN
SOUT
First Data
Data
Last Data
First Data
Data
Last Data
2
(CPOL=0)
(CPOL=1)
Figure 20. DSPI modified transfer format timing — master, CPHA = 0
Communication modules
S32V234 Data Sheet, Rev. 8, 01/2019
42 NXP Semiconductors