Datasheet

Communication modules
6.5.1 DSPI timing
Measurements are with a load of 45 pF on output pins. Input slew = 1 ns,
SIUL2_MSCRn[DSE] = 101, and SIUL2_MSCRn[SRE] = 11.
NOTE
These are not necessarily the default configuration after chip
resets. You must ensure the above chip configuration to match
the measurements in this section.
Table 36. DSPI timing
No. Symbol Parameter Conditions Min Max Unit
1 t
SCK
DSPI cycle time Master (MTFE = 0) 40
1
- ns
Slave (MTFE = 0) 40 -
Slave Receive Only Mode
2
16 -
2 t
CSC
PCS to SCK delay - 16
3
- ns
3 t
ASC
After SCK delay - 16
4
- ns
4 t
SDC
SCK duty cycle - t
SCK
/2 - 1.5 t
SCK
/2 + 1.5 ns
5 t
A
Slave access time SS active to SOUT valid - 40 ns
6 t
DIS
Slave SOUT disable
time
SS inactive to SOUT High-Z
or invalid
- 15 ns
7 t
PCSC
PCSx to PCSS time - 13 - ns
8 t
PASC
PCSS to PCSx time - 13 - ns
9 t
SUI
Data setup time for
inputs
Master (MTFE = 0) 15 - ns
Slave 2 -
Master (MTFE = 1, CPHA = 0) 6 -
Master (MTFE = 1, CPHA = 1) 20 -
10 t
HI
Data hold time for
inputs
Master (MTFE = 0) -4 - ns
Slave 4 -
Master (MTFE = 1, CPHA = 0) 11 -
Master (MTFE = 1, CPHA = 1) -4 -
11 t
SUO
Data valid (after SCK
edge)
Master (MTFE = 0) - 4 ns
Slave - 16
Master (MTFE = 1, CPHA = 0) - 12
Master (MTFE = 1, CPHA = 1) - 4
12 t
HO
Data hold time for
outputs
Master (MTFE = 0) -2 - ns
Slave 3 -
Master (MTFE = 1, CPHA = 0) 5 -
Master (MTFE = 1, CPHA = 1) -2 -
6.5
Communication modules
S32V234 Data Sheet, Rev. 8, 01/2019
NXP Semiconductors 39