Datasheet

6.4.4 LPDDR2 timing parameter
Figure 13. LPDDR2 command and address timing parameter
NOTE
RESET pin has a external weak pull DOWN requirement if
LPDDR2 memory is NOT required to support content retention
in the device low power modes where core voltage is off but
DRAM voltage is on.
NOTE
RESET pin has a external weak pull UP requirement if
LPDDR2 memory is required to support content retention in the
device low power modes where core voltage is off but DRAM
voltage is on.
NOTE
CKE pin has a external weak pull down requirement.
NOTE
LPDDR2 timing parameters are compliant with JESD209-2B
specification.
Table 33. LPDDR2 timing parameter
ID Parameter Symbol CK = 533 MHz Unit
Min Max
LP1 SDRAM clock high-level width tCH (avg) 0.45 0.55 tCK (avg)
LP2 SDRAM clock LOW-level width tCL (avg) 0.45 0.55 tCK (avg)
LP3 CS, CKE setup time tIS 235 — ps
LP4 CS, CKE hold time tIH 250 — ps
LP3 CA setup time tIS 235 — ps
LP4 CA hold time tIH 250 — ps
Memory interfaces
S32V234 Data Sheet, Rev. 8, 01/2019
36 NXP Semiconductors