Datasheet

6.4.3 DDR3 and DDR3L write cycle
Figure 12. DDR3 and DDR3L write cycle
Table 32. DDR3 and DDR3L write cycle
ID Parameter Symbol CK = 533 MHz Unit
Min Max
DDR17 DQ and DQM setup time to DQS
(differential strobe)
tDS 206 — ps
DDR18 DQ and DQM hold time to DQS
(differential strobe)
tDH 280 — ps
DDR21 DQS latching rising transitions to
associated clock edges
tDQSS -0.25 +0.25 tCK (avg)
DDR22 DQS high level width tDQSH 0.45 0.55 tCK (avg)
DDR22 DQS low level width tDQSL 0.45 0.55 tCK (avg)
NOTE
To receive the reported setup and hold values, write calibration
should be performed in order to locate the DQS in the middle of
DQ window.
NOTE
All measurements are in reference to Vref level.
NOTE
Measurements were done using balanced load and 25 ohms
resistor from outputs to VDD_REF.
Memory interfaces
S32V234 Data Sheet, Rev. 8, 01/2019
NXP Semiconductors 35