Datasheet

6.4.2 DDR3 and DDR3L read cycle
Figure 11. DDR3 and DDR3L read cycle
Table 31. DDR3 and DDR3L read cycle
ID Parameter Symbol CK = 533 MHz Unit
Min Max
DDR26 Minimum required DQ valid
window width
— 563 — ps
NOTE
To receive the reported setup and hold values, read calibration
should be performed in order to locate the DQS in the middle of
DQ window.
NOTE
All measurements are in reference to Vref level.
NOTE
Measurements were done using balanced load and 25 ohms
resistor from outputs to VDD_REF
Memory interfaces
S32V234 Data Sheet, Rev. 8, 01/2019
34 NXP Semiconductors