Datasheet

Table 26. QuadSPI input timing (DDR mode) specifications
Symbol Parameter Value Unit Configuration
Min Max
T
is
Setup time for incoming data 2.5 @ 3.3 V
2 @ 1.8 V
— ns —
T
ih
Hold time for incoming data 1.5 — ns —
F
SCK
SCK Clock Frequency — 50 (Internal DQS)
@ 3.3 V
56 (Internal DQS)
@ 1.8 V
MHz See Table 23
1 2 3
Tck
Tov
Toh
Clock
SCK
CS
Data out
Figure 7. QuadSPI output timing (DDR mode) diagram
Table 27. QuadSPI output timing (DDR mode) specifications
Symbol Parameter Value Unit
Min Max
T
ov
Output Data Valid — 1/(4*F
SCK
) + 1.5 ns
T
oh
Output Data Hold 1/(4*F
SCK
)
- 1.5
— ns
HyperFlash mode
Maximum clock frequency = 100 MHz.
Memory interfaces
S32V234 Data Sheet, Rev. 8, 01/2019
NXP Semiconductors 29