Datasheet

1 2 3
Toh
Tov
Tck
Tcss
Tcsh
Clock
SCK
CS
Data out
Figure 5. QuadSPI output timing (SDR mode) diagram
Table 25. QuadSPI output timing (SDR mode) specifications
Symbol Parameter Value Unit
Min Max
T
ov
Output Data Valid — 1.5 ns
T
oh
Output Data Hold –1.5 — ns
F
SCK
SCK clock frequency — 104 MHz
T
css
Chip select output setup time 2 — ns
T
csh
Chip select output hold time 1 — ns
NOTE
For any frequency setup and hold specifications of the memory
should be met.
DDR mode
1 2 3
Tck
Tis
Tih
Clock
SCK
CS
Data in
Figure 6. QuadSPI input timing (DDR mode) diagram
Memory interfaces
S32V234 Data Sheet, Rev. 8, 01/2019
28 NXP Semiconductors