Datasheet

1 2 3
Tck
Tis
Tih
Clock
SCK
CS
Data in
Figure 4. QuadSPI input timing (SDR mode) diagram
NOTE
• A negative time indicates the actual capture edge inside the
device is earlier than clock appearing at pad.
• All board delays need to be added appropriately
• Input hold time being negative does not have any
implication or max achievable frequency
Table 24. QuadSPI input timing (SDR mode) specifications
Symbol Parameter Value Unit
Min Max
T
is
Setup time for incoming data 2.5 — ns
T
ih
Hold time for incoming data 1 — ns
F
SCK
SCK clock frequency — 104 MHz
Memory interfaces
S32V234 Data Sheet, Rev. 8, 01/2019
NXP Semiconductors 27