Datasheet

Memory interfaces
6.3.1 QuadSPI AC specifications
• Measurements are with a load of 35 pF on output pins. Input slew: 1 ns,
SIUL2_MSCRn[DSE] = 111, and SIUL2_MSCRn[SRE] = 11
• QuadSPI input timing is with 15 pF load on flash output.
• QuadSPI_MCR[DQS_EN] must be set as 1 for SDR READ
NOTE
These are not necessarily the default configuration after chip
resets. You must ensure the above chip configuration to match
the measurements in this section.
The following table lists various QuadSPI modes and their corresponding configurations.
Please refer to the device Reference Manual for register and bit descriptions.
Table 23. QuadSPI read/write settings
Modes supported by
QuadSPI
QuadSPI_
MCR[DDR
_EN]
QuadSPI_
MCR[DQS
_EN]
QuadS
PI_MC
R
[DQS_
CD]
Quad
SPI_M
CR
[REF
CLK_
SEL]
QuadSP
I_MCR
[DQS_M
DSL]
QuadSPI_SO
CCR
[FDCC_FB]
QuadSPI_SO
CCR
[FDCC_FA]
QuadSPI_
FLSHCR[
TDH]
SDR mode Internal
DQS mode
0 1 000 1 1 39h @ 3.3 V
3Fh @ 1.8 V
39h @ 3.3 V
3Fh @ 1.8 V
00
DDR mode Internal
DQS mode
1 1 000 0 1 4Ah @ 3.3 V
50h @ 1.8 V
4Ah @ 3.3 V
50h @ 1.8 V
01
External
DQS mode
(supported
by
HyperFlas
h)
1 1 000 0 0 00h 00h 01
SDR mode
For SDR mode, QuadSPI_MCR[DQS_EN] must be set as '1'.
6.3
Memory interfaces
S32V234 Data Sheet, Rev. 8, 01/2019
26 NXP Semiconductors