Datasheet

4. STEPSIZE x STEPNO < 18432
For the PLL frequencies supported by this device, refer to the Table - "PLL frequencies"
in the "Clocking" chapter of the Reference Manual.
6.2.4 DFS electrical specifications
DFS takes input clock from PLL output. Here is relation between input and output clock
of each phase divider:
F(dfsclkout) = F(dfsclkin)/[mfi+(mfn/256)]
mfi : integer part of division [1:255]
mfn: Fractional part of division [1:255]
Table 21. DFS electrical specification
1
Parameter Min Typical Max Unit
Input Frequency 800 — 1066 MHz
Period jitter — — 300 ps
TIE — — 600 ps
1. DFSes mfi, mfn and frequencies are defined and restricted as per Reference Manual. See the table "DFS (mfi, mfn)
settings" in the "Clocking" chapter of the Reference Manual for the supported mfi and mfn combinations.
6.2.5 LFAST PLL Electrical Specifications
The following table lists AC specification of the LFAST PLL block.
Table 22. LFAST PLL Interface AC
Specifications
Parameter Min Typical Max Unit
PLL input clock 10 — 26 MHz
PLL VCO Frequency 312 — 320 MHz
Phase Lock time — — 50 µs
RMS Period Jitter — — 40
1
ps
Long Term Jitter
2
Random Jitter
— 84 — ps
Deterministic Jitter — 80 — ps
Total Jitter @ BER 10
-9
— 1.09 1.31
3
ns
1. When SysClk = 26 MHz
2. VCO clock measured over 100 µs acquisition at ZipWire TX LVDS across 100 ohm load
3. Only Total Jitter is given a maximum specification as variation of Random and Deterministic jitter is not critical. Any
combined Random and Deterministic jitter yielding a Total Jitter @ 10
-9
BER is within maximum specification and is
acceptable
Clocks and PLL interfaces modules
S32V234 Data Sheet, Rev. 8, 01/2019
NXP Semiconductors 25