Datasheet

1. The start-up time is dependent upon crystal characteristics, board leakage, etc, high ESR and excessive capacitive loads
can cause long start-up time
Following crystals are used in internal crystal oscillator validation:
• NX3225 – 40 MHz; Load capacitance = 8 pF
• NX5032 – 40 MHz; Load capacitance = 8 pF
6.2.2 48 MHz FIRC electrical characteristics
Table 19. FIRC electrical specifications
Symbol Parameter Conditions Value Unit
Min Typ Max
F
Target
FIRC target
frequency
(trimmed)
— — 48 — MHz
δF
var_T
FIRC frequency
variation with
respect to
supply and
temperature
after process
trimming
— -10 — +10 %
6.2.3 PLL electrical specifications
Table 20. PLL electrical characteristics
1
Symbol Parameter Conditions Value Unit
Min Typ Max
f
PLLIN
PLL input clock
2
— 20
3
— 40
3
MHz
Δ
PLLIN
PLL input clock duty cycle
2
— 40 — 60 %
t
PLLLOCK
PLL lock time — — — 100 µs
Δ
PLLT
Period jitter — — — 150 ps
Δ
PLLTIE
TIE — — — 560 ps
f
PLLMOD
SSCG modulation frequency — — — 32 kHz
δ
PLLMOD
SSCG modulation depth (Down
Spread)
— 0.50 — 2.7
4
%
1. The jitter values are gauranteed for following conditions:
1. Measurement being done on LFAST TX pad with observed frequency greater than 250 M and less than 320 M
2. Minimum SOC activity - Operations required to observe clock must be functional.
3. Maximum frequency change in SSCG modulation is limited by following relation: Modulation Depth * VCO Frequency
< PLL Reference (PFD) Frequency
2. PLL0IN clock retrieved from either internal RCOSC or external FXOSC clock. Input characteristics are granted when using
internal RCOSC or external oscillator is used in functional mode.
3. The PLLIN clock is the frequency after the PREDIV(Pre-divider) value division, and before the Phase detector block.
Please refer to the PLLs section of clocking chapter in the Reference Manual.
Clocks and PLL interfaces modules
S32V234 Data Sheet, Rev. 8, 01/2019
24 NXP Semiconductors