Datasheet
1. Please see description of Clock & reset section in ADC chapter in Reference Manual for details. User need to generate
AD_clk = 40 MHz for 0.5 MSPS operation. For example, if f
ck
= 80 MHz, configure MCR[8].ADCLKSE = 0 and
MCR[4].ADCLKDIV = 0 (default).
2. During the sample time the input capacitance CS can be charged/discharged by the external source. The internal
resistance of the analog source must allow the capacitance to reach its final voltage level within t
sample
. After the end of the
sample time t
sample
, changes of the analog input voltage have no effect on the conversion result. Values for the sample
clock t
sample
depend on programming. For internal ADC channels, the minimum sampling time required is 3 microsecond.
3. This parameter does not include the sample time t
sample
, but only the time for determining the digital result and the time to
load the result register with the conversion result.
4. Specifications are quoted here for input signal ranging from 150 mV to VDD_HV_ADC - 150 mV. For signals outside this
range, the Specifications may degrade beyond limits specified in this table.
6.1.2 Thermal Monitoring Unit (TMU)
The following table describes TMU electrical characteristics.
Table 17. TMU electrical characteristics
Symbol Parameter Conditions Value Unit
Min Typ Max
T
j
Temperature monitoring
range
— -40 — 125 °C
T
SENS
Sensitivity — — 2.5 — mV/°C
T
ACC
Accuracy T
J
= -40 °C to 40 °C -10 — +10 °C
T
J
= 40 °C to 125 °C -6 — +6 °C
Clocks and PLL interfaces modules
6.2.1
Main oscillator electrical characteristics
The device provides an oscillator/resonator driver of a Pierce-type structure.
Table 18. Main oscillator electrical characteristics
Symbol Parameter Conditions Value Unit
Min Typ Max
f
FXOSCHS
Oscillator frequency — — 40.0 n/a MHz
T
FXOSCHSSU
Oscillator start-up time f
FXOSCHS
= 40 MHz — — 2
1
ms
V
IH
Input high level CMOS
Schmitt Trigger
Vref =
0.5*VDD_HV_FXOSC
where VDD_HV_FXOSC
is FXOSC HV Supply
Vref+0.5 — VDD_HV_FXOS
C
V
V
IL
Input low level CMOS
Schmitt Trigger
Vref =
0.5*VDD_HV_FXOSC
where VDD_HV_FXOSC
is FXOSC HV Supply
0 — Vref – 0.5 V
6.2
Clocks and PLL interfaces modules
S32V234 Data Sheet, Rev. 8, 01/2019
NXP Semiconductors 23