Datasheet

• Memory interfaces
– 32-bit DRAM Controller with support for LPDDR2/DDR3/DDR3L - Data rate of up to 1066 MT/s at 533 MHz clock
frequency with ECC (SEC-DED-TED) triple error detection support for subregion
– QuadSPI supporting Execute-In-Place (XIP)
– Boot flash fault detection and correction using two-dimensional parity.
– Triple fault detection and single fault correction scheme for external DDR-RAM including address/page fault detection.
• Video input interfaces, Image processing, graphics processing, display
– Display Control Unit (2D-ACE) with 24-bit RGB, GPU frame buffer decoding
– GPU GC3000 with frame buffer compression
– 2x VIU (Video interface unit) for camera input
– 2x MIPICSI2 with four lanes for camera input (support 1080 pixel @ 30 fps)
– Image signal processor (ISP), supporting 2x1 or 1x2 megapixel @ 30 fps and 4x2 megapixel for subset of functions
(exposure control, gamma correction)
– 2x APEX2-CL Image cognition processor. APEX-642CL comprises two Array Processing Unit (APU) cores
configurable as single SIMD engine with 64 16-bit Computational Units (CU), or configurable as two core MIMD
engines with 32 16-bit CUs each.
– CUs are comprised of four Functional Units: 16-bit Multiplier, Load Store Unit, ALU, and Shifter
– JPEG video decoder (8/12-bit)
– H.264 video decoder (8/10/12-bit), High-intra and constrained baseline formats
– H.264 video encode (8/10/12-bit), High-intra only
– Fast DMA for data transfers between DRAM and System RAM with CRC
• Human-Machine Interface (HMI)
– GPIO pins with interrupt support, DMA request capability, digital glitch filter
– Configurable slew rate and drive strength on all output pins
• System RAM
– 4 MB On-Chip System RAM with ECC
S32V234 Data Sheet, Rev. 8, 01/2019
2 NXP Semiconductors