Datasheet

• Address/Cmd to be routed within 66 mils with respect to CLK and to be matched
from controller to memory; memory to memory as well
• All traces to be routed in internal layers
• Preference is to use only two layers for routing this group
• Limit the via number to less than three
NOTE
The differential clock lines on the DDR3 interface should
use AC termination scheme, with a 0.1 µF series capacitor
and referenced to DDR IO supply (V
DD_DDR_IO
).
• Data/Strobe
• Route with 50 ohm controlled impedance and differential pair (DQS strobe) with
100 ohm controlled impedance
• Data to be routed within 33 mils with respect to respective strobe
• To be referenced with Ground
• All traces to be routed in internal layers
• Strictly to be routed in only two layers
• Avoid more than two vias
LPDDR2 PCB design
• CLK/Addess/Commands
• Route with 50 ohm controlled impedance and differential pair (CLK) with 100
ohm controlled impedance
• To be referenced with Power, not Ground
• Address/Cmd to be routed within 66 mils with respect to CLK and to be matched
from controller to memory
• All traces to be routed in internal layers and delay should be less than 150 ps
• Preference is to use only two layers for routing this group
• Limit the via number to less than three
• Data/Strobe
• Route with 50 ohm controlled impedance and differential pair (DQS strobe) with
100 ohm controlled impedance
• Data to be routed within 33 mils with respect to respective strobe
• To be referenced with Ground
• All traces to be routed in internal layers and delay should be less than 150 ps
• Strictly to be routed in only two layers
• Avoid more than two vias
GPIO Interfaces
• QuadSPI
• Put 22 ohm series termination on board when operating with
SIUL2_MSCRn[DSE] 111
General
S32V234 Data Sheet, Rev. 8, 01/2019
14 NXP Semiconductors