Datasheet

Table 6. Power consumption (continued)
Parameter Description Max Values
125C T
j
105C T
j
S32V232BM Device in reset 6.0 A 4.5 A
S32V234CO Device in reset 6.4 A 4.8 A
S32V234CK Device in reset 4.8 A 3.5 A
S32V232BL Device in reset 2.7 A 2.0 A
S32V232CK Device in reset 4.4 A 3.2 A
VDD_LV_CORE (Dynamic) 4x A53 CPU with Dhrystone
MIPS running on each CPU
@1 GHz
3
1.4 A
VDD_HV_CSI Current for both MIPICSI2
interfaces operating as per
1) RX Operation at 1.5 Gbps
per MIPICSI2
2) MIPICSI2 not used (IP
Powered and Disabled)
1) 10 mA
2) 1 mA
VDD_LV_CSI Current for both MIPICSI2
interfaces operating as per
1) RX Operation at 1.5 Gbps
per MIPICSI2
2) MIPICSI2 not used (IP
Powered and Disabled)
1) 40 mA
2) 13 mA
VDD_HV_PLL All five PLLs operating at 1
GHz VCO frequency
35 mA
VDD_HV_LFASTPLL Use case:
1) PLL operating with 320
MHz (LFAST used)
2) PLL not operational
(LFAST not used)
1) 26 mA
2) .1 mA
VDD_HV_FXOSC Shared supply for FXOSC
operating with 40 MHz crystal
and FIRC oscillator
5 mA
VDD_HV_PMC As per default usage (no use
case differentiation)
10 mA
VDD_HV_EFUSE Use case:
1) eFuse programming
happening
1) 10 mA
VDD_LV_PLL All five PLLs operating at 1
GHz VCO frequency
80 mA
PCIE_VP Use case:
1) 5 GHz operation (PCIe 2.0)
2) Reset/idle
1) 80 mA
2) 30 mA
PCIE_VPH Use case:
1) 5 GHz operation (PCIe 2.0)
1) 50 mA
2) 20 mA
Table continues on the next page...
General
S32V234 Data Sheet, Rev. 8, 01/2019
12 NXP Semiconductors