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S32V234

S32V234 Data Sheet

Features

• ARM® Cortex®-A53, 64-bit CPU

– Up to 1000 MHz Quad ARM Cortex-A53

– 32 KB/32 KB I-/D- L1 Cache

– NEON MPE co-processor

– Dual precision FPU

– 2 clusters with 2 CPUs and 256 KB L2 cache each

– Memory Management Unit

– GIC Interrupt Controller

– ECC/parity error support for its memories

– Generic timers

– Fault encapsulation by hardware for redundant

executed application software on multiple core

cluster

• ARM Cortex-M4, 32-bit CPU

– Up to 133 MHz

– 16 KB/16 KB I-/D- L1 Cache

– 32+32 KB tightly coupled memory (TCM)

– ECC/parity support for its memories

• Clocks

– Phase Locked Loops (PLLs)

– 1 external crystal oscillator (FXOSC)

– 1 FIRC oscillator

• System protection and power management features

– Flexible run modes to consume low power based on

application needs

– Peripheral clock enable register can disable clocks to

unused modules, thereby reducing currents

– Power gating of unused A53 cores and GPU

– Low and high voltage warning and detect

– Hardware CRC module to support fast cyclic

redundancy checks (CRC)

– 120-bit unique chip identifier

– Hardware watchdog

– eDMA controller with 32 channels (with

DMAMUX)

– Extended Resource Domain Controller

• Safety concept

– ISO 26262, ASIL level target

– Measures to detect faults in memory and logic

– Measures to detect single point and latent faults

– Quantitative out of context analysis of functional

safety (FMEDA) tailored to application specifics

– Safety manual and FMEDA report available

• Security

– CSE with 16 KB of on-chip Secure RAM and ROM.

– Secure vs non-secure applications separation

supported via ARM v8 exception level support in

the ARM Cortex A53 clusters and its extension via

XRDC on chip level.

– Boot from NOR flash with AES-128 (CTR)

– On-Chip One-Time Programmable element

Controller (OCOTP_CTRL) with on chip electrical

fuse array.

– System JTAG Controller (SJC)

• Debug functionality

– Standard JTAG and Compact JTAG

– 16-bit Trace port, Serial Wire Output port

• Timers

– General purpose timers (FTM)

– Two Periodic Interrupt Timer (PIT)

– IEEE 1588 Timers (part of Ethernet Subsystem)

• Analog

– 1x 12-bit 1.8 V SAR ADC with self-test

• Communications

– UART(w/ LIN2.1l)

– Serial peripheral interface (SPI)

– I2C blocks

– PCI express 2.0 with endpoint and root complex

support

– LFAST serial link

– 1 GBit Ethernet with PTP IEEE 1588

– FD-CAN

– FlexRay Dual Channel, Version 2.1 RevA

NXP Semiconductors

Document Number S32V234

Data Sheet: Technical Data

Rev. 8, 01/2019

NXP reserves the right to change the production detail specifications as may be

required to permit improvements in the design of its products.

Summary of content (90 pages)

PAGE 1
NXP Semiconductors Data Sheet: Technical Data Document Number S32V234 Rev.
PAGE 2
• Memory interfaces – 32-bit DRAM Controller with support for LPDDR2/DDR3/DDR3L - Data rate of up to 1066 MT/s at 533 MHz clock frequency with ECC (SEC-DED-TED) triple error detection support for subregion – QuadSPI supporting Execute-In-Place (XIP) – Boot flash fault detection and correction using two-dimensional parity. – Triple fault detection and single fault correction scheme for external DDR-RAM including address/page fault detection.
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Table of Contents 1 Block diagram.................................................................................... 5 2 Family comparison.............................................................................5 2.1 3 4 5 Feature Set...............................................................................5 Memory interfaces...................................................................26 6.3.1 6.4 QuadSPI AC specifications.......................................
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6.6.1.1 Interface to TFT panels..........................61 6.6.1.2 Interface to TFT LCD Panels—Pixel 6.10 External interrupt timing (IRQ pin)........................................ 74 7 Level Timings........................................ 62 6.6.1.3 Interface to TFT LCD panels—access 7.1 8 level........................................................63 6.6.2 Video input unit (VIU) timing specifications............64 6.6.3 MIPICSI2 D-PHY electrical and timing parameters.65 6.6.3.
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Block diagram 1 Block diagram XRDC SEQ 128bits MC XRDC 128bits 4KB PRAM 64KB CRAM 16KB KRAM MC Sequencer Debug MIPI-CSI2 MIPI-CSI2 ISP0 ISP1 ISP2 ••• ISPN H.264 Encoder H.264 Decoder JPEG Decoder 128bits 64bits 128-bits 128-bits 128bits 64bits Hierarchical NIC 301 AXI Bus System incl.
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Family comparison Table 1.
PAGE 7
Family comparison Table 1. Feature Set (continued) Feature S32V234 S32V232 • Two Periodic Interrupt Timer (PIT) • IEEE 1588 Timers (part of Ethernet Subsystem) Communications • • • • UART(w/ LIN2.1l) Serial peripheral interface (SPI) I2C blocks PCI express 2.0 with endpoint and root complex support LFAST serial link 1 GBit Ethernet with PTP IEEE 1588 FD-CAN Flexray Dual Channel, Version 2.
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Ordering parts Table 1. Feature Set Feature S32V234 S32V232 • Frequency scaling and clock gating for processing blocks and peripherals in run mode 3 Ordering parts 3.1 Ordering information An example of orderable part numbers of this chip are in the table below: Table 2. Ordering information Part number ISP GPU CSE Low power (leakage based) No.
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General Table 3. Operation above maximum operating conditions (continued) Core Voltage Domain Electrical Specifications Value Conditions Junct Temp Absolute Maximum Supply Voltage 1.29 V < 60 s 25 °C Absolute Maximum Supply Voltage 1.1 V < 10 hr 25 °C Operating Max Supply Voltage 1.05 V — — Electrical Specifications Value Conditions Junct Temp Absolute Maximum Supply Voltage 4.95 V < 60 s 25 °C Absolute Maximum Supply Voltage 4.29 V < 10 hr 25 °C Operating Max Supply Voltage 3.
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General Table 4. Recommended operating conditions (continued) Symbol Parameter Conditions Min Max Unit VDD_HV_PMC, VDDIO_LFAST, VDD_HV_EFUSE, VDD_HV_DDR VDD_LV_PLL 1.0 V supply voltage (for analog circuits, PLLs) — 0.95 1.05 V VREFH_ADC 1.8 V ADC high reference voltage — 1.71 1.95 V VDD_HV_ADV 1.8 V ADC supply voltage — 1.71 1.95 V VSS_HV_ADV ADC ground and low reference voltage — 0 0 V VREFL_ADC 1.
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General Table 5.
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General Table 6. Power consumption (continued) Parameter Description Max Values 125C Tj 105C Tj S32V232BM Device in reset 6.0 A 4.5 A S32V234CO Device in reset 6.4 A 4.8 A S32V234CK Device in reset 4.8 A 3.5 A S32V232BL Device in reset 2.7 A 2.0 A S32V232CK Device in reset 4.4 A 3.2 A VDD_LV_CORE (Dynamic) 4x A53 CPU with Dhrystone MIPS running on each CPU @1 GHz3 1.4 A VDD_HV_CSI Current for both MIPICSI2 interfaces operating as per 1) 10 mA 2) 1 mA 1) RX Operation at 1.
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General Table 6. Power consumption (continued) Parameter Description Max Values 125C Tj 105C Tj 2) Reset/idle VDD_HV_ADV ADC operational 1 mA VDD_REFH_ADC Voltage reference for ADC 80 μA 1. Data represented is at 125 °C Tj and 1.01 V vdd conditions 2. Includes SoC, GPU, and ARM supply combinations depending on use case description. 3. Adder to the static idd current component.
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General • Address/Cmd to be routed within 66 mils with respect to CLK and to be matched from controller to memory; memory to memory as well • All traces to be routed in internal layers • Preference is to use only two layers for routing this group • Limit the via number to less than three NOTE The differential clock lines on the DDR3 interface should use AC termination scheme, with a 0.1 µF series capacitor and referenced to DDR IO supply (VDD_DDR_IO).
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I/O parameters • TRACE • Put 22 ohm series termination on board when operating with SIUL2_MSCRn[DSE] 111 • ENET • Put 22 ohm series termination on board when operating with SIUL2_MSCRn[DSE] 111 5 I/O parameters 5.1 General purpose I/O parameters 5.1.1 GPIO speed at various voltage levels NOTE Rise/fall times numbers in Datasheet are guaranteed by design; to obtain actual rise/fall times parameters with specific packages and boards, use appropriate I/O IBIS model. Table 8. GPIO rise/fall times (1.
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General purpose I/O parameters Table 9. GPIO rise/fall times (2.5 V range) Parameter Symbol IO output tpr transition time, rise/fall1 Drive strength SIUL2_MSCRn[D SE] 001 Slew rate slow fast 010 011 100 101 111 Test conditions Typ 15 pF Cload on pad Max 7.41/8.22 Unit ns 7.36/8.16 slow 3.30/3.74 fast 2.76/3.38 slow 3.44/3.04 fast 2.75/2.55 slow 4.05/3.54 fast 3.56/2.97 slow 3.39/2.93 fast 2.72/2.47 slow 2.31/2.03 fast 1.80/1.75 1. Max condition for tpr: wcs model, 0.
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General purpose I/O parameters NOTE The maximum rise time for all GPIO pins is 1 ms. Input pins do not support hysteresis, therefore very slow ramps (like the ones generated by an RC circuit with a large RC value) can induce bounces in the input read state during the transition from logic low to logic high or vice versa. 5.1.2 DC electrical specifications Table 11. DC electrical specifications Symbol Parameter Test conditions Min Typ Max Unit Voh High-level output voltage Ioh=-100 μA ovdd1-0.
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General purpose I/O parameters 5.2 DDR pads 5.2.1 DDR3 mode 5.2.1.1 DDR3 mode DC electrical specifications Table 13. DDR3 mode DC electrical specifications Parameter Symbol Test conditions Min Typ Max Unit High-level output voltage Voh Ioh=-100 μA 0.8*ovdd — — V Low-level output voltage Vol Iol=100 μA — — 0.2*ovdd V High-level DC input voltage Vih (DC) — Vref + 0.2 — ovdd V High-level DC input voltage Vil (DC) — ovss — Vref - 0.2 V Input reference voltage Vref — 0.
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LPDDR2 mode Table 14. DDR3L mode DC electrical specifications (continued) Parameter Symbol Test conditions Min Typ Max Unit Input reference voltage Vref — 0.49*ovdd 0.5*ovdd 0.51*ovdd V Vref current draw Icc-vref — — — 1 mA Termination voltage Vtt — 0.49*ovdd 0.5*ovdd 0.
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Peripheral operating requirements and behaviors NOTE External pull up/down resistors must be used on the BOOTMOD pins in order to ensure latching at the correct state. NOTE NXP would anticipate that most customers would use the boot from fuses option in a production environment. However, there is no reliability impact if the device is configured by RCON rather than fuses. 6 Peripheral operating requirements and behaviors 6.1 Analog modules 6.1.
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Analog modules Offset Error OSE Gain Error GE 4095 4094 4093 4092 4091 4090 ( 2) code out 7 ( 1) 6 5 (5) 4 (4) 3 (3) 2 1 1 LSB ideal = (VrefH-VrefL)/4096 = 1.8V/4096 = . 439mV Total Unadjusted Error TUE = +/-10 LSB = +/-4.
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Analog modules 6.1.1.1 Input equivalent circuit EXTERNAL CIRCUIT INTERNAL CIRCUIT SCHEME VDD Source Filter RS Current Limiter RF Sampling RSW1 RAD RL CF VA Channel Selection CP1 CS CP2 RS Source Impedance RF Filter Resistance CF Filter Capacitance RL Current Limiter Resistance RSW1 Channel Selection Switch Impedance RAD Sampling Switch Impedance CP Pin Capacitance (two contributions, CP1 and CP2) CS Sampling Capacitance Figure 3. Input equivalent circuit Table 16.
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Clocks and PLL interfaces modules 1. Please see description of Clock & reset section in ADC chapter in Reference Manual for details. User need to generate AD_clk = 40 MHz for 0.5 MSPS operation. For example, if fck = 80 MHz, configure MCR[8].ADCLKSE = 0 and MCR[4].ADCLKDIV = 0 (default). 2. During the sample time the input capacitance CS can be charged/discharged by the external source. The internal resistance of the analog source must allow the capacitance to reach its final voltage level within tsample.
PAGE 24
Clocks and PLL interfaces modules 1. The start-up time is dependent upon crystal characteristics, board leakage, etc, high ESR and excessive capacitive loads can cause long start-up time Following crystals are used in internal crystal oscillator validation: • NX3225 – 40 MHz; Load capacitance = 8 pF • NX5032 – 40 MHz; Load capacitance = 8 pF 6.2.2 48 MHz FIRC electrical characteristics Table 19.
PAGE 25
Clocks and PLL interfaces modules 4. STEPSIZE x STEPNO < 18432 For the PLL frequencies supported by this device, refer to the Table - "PLL frequencies" in the "Clocking" chapter of the Reference Manual. 6.2.4 DFS electrical specifications DFS takes input clock from PLL output. Here is relation between input and output clock of each phase divider: F(dfsclkout) = F(dfsclkin)/[mfi+(mfn/256)] mfi : integer part of division [1:255] mfn: Fractional part of division [1:255] Table 21.
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Memory interfaces 6.3 Memory interfaces 6.3.1 QuadSPI AC specifications • Measurements are with a load of 35 pF on output pins. Input slew: 1 ns, SIUL2_MSCRn[DSE] = 111, and SIUL2_MSCRn[SRE] = 11 • QuadSPI input timing is with 15 pF load on flash output. • QuadSPI_MCR[DQS_EN] must be set as 1 for SDR READ NOTE These are not necessarily the default configuration after chip resets. You must ensure the above chip configuration to match the measurements in this section.
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Memory interfaces 1 2 3 Clock Tck SCK CS Tis Tih Data in Figure 4. QuadSPI input timing (SDR mode) diagram NOTE • A negative time indicates the actual capture edge inside the device is earlier than clock appearing at pad. • All board delays need to be added appropriately • Input hold time being negative does not have any implication or max achievable frequency Table 24. QuadSPI input timing (SDR mode) specifications Symbol Parameter Value Min Unit Max Tis Setup time for incoming data 2.
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Memory interfaces 1 2 3 Clock Tck SCK Tcsh Tcss CS Toh Tov Data out Figure 5. QuadSPI output timing (SDR mode) diagram Table 25. QuadSPI output timing (SDR mode) specifications Symbol Parameter Value Min Unit Max Tov Output Data Valid — 1.5 ns Toh Output Data Hold –1.5 — ns FSCK SCK clock frequency — 104 MHz Tcss Chip select output setup time 2 — ns Tcsh Chip select output hold time 1 — ns NOTE For any frequency setup and hold specifications of the memory should be met.
PAGE 29
Memory interfaces Table 26. QuadSPI input timing (DDR mode) specifications Symbol Parameter Value Unit Min Tis Setup time for incoming data Tih Hold time for incoming data FSCK SCK Clock Frequency Configuration Max 2.5 @ 3.3 V — ns — — ns — 2 @ 1.8 V 1.5 — 50 (Internal DQS) MHz @ 3.3 V See Table 23 56 (Internal DQS) @ 1.8 V 1 2 3 Clock Tck SCK CS Tov Toh Data out Figure 7. QuadSPI output timing (DDR mode) diagram Table 27.
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Memory interfaces RDS TsMIN ThMIN DI[7:0] Figure 8. QuadSPI input timing (HyperFlash mode) diagram Table 28. QuadSPI input timing (HyperFlash mode) specifications Symbol Parameter Value Min Unit Max TsMIN Setup time for incoming data 0.950 — ns ThMIN Hold time for incoming data 0.950 — ns CK CK 2 Tclk SKMAX Tclk SKMIN THO TDVO Output Invalid Data Figure 9. QuadSPI output timing (HyperFlash mode) diagram Table 29.
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Memory interfaces Table 29. QuadSPI output timing (HyperFlash mode) specifications (continued) Symbol Parameter Value Min Unit Max TclkSKMAX Ck to Ck2 skew max — T/4 + 0.150 ns TclkSKMIN Ck to Ck2 skew min T/4 – 0.150 — ns 6.4 DDR SDRAM Specific Parameters (DDR3, DDR3L, and LPDDR2) 6.4.1 DDR3 and DDR3L timing parameters NOTE Operating voltages of DDR3 and DDR3L are different. S32V234 Data Sheet, Rev.
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Memory interfaces Figure 10. DDR3 and DDR3L command and address timing parameters NOTE RESET pin has an external weak pull DOWN requirement if DDR3 memory is NOT required to support content retention in the device low power modes where core voltage is off but DRAM voltage is on. NOTE RESET pin has an external weak pull UP requirement if DDR3 memory is required to support content retention in the device low power modes where core voltage is off but DRAM voltage is on.
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Memory interfaces NOTE DDR3 and DDR3L timing parameters are compliant with JESD79-3F and JESD79-3-1A.01 specifications respectively. Table 30. DDR3 and DDR3L timing parameter ID Parameter Symbol CK = 533 MHz Unit Min Max DDR1 CK clock high-level width tCH 0.47 0.53 tCK (avg) DDR2 CK clock low-level width tCL 0.47 0.
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Memory interfaces 6.4.2 DDR3 and DDR3L read cycle Figure 11. DDR3 and DDR3L read cycle Table 31. DDR3 and DDR3L read cycle ID DDR26 Parameter Minimum required DQ valid window width Symbol — CK = 533 MHz Unit Min Max 563 — ps NOTE To receive the reported setup and hold values, read calibration should be performed in order to locate the DQS in the middle of DQ window. NOTE All measurements are in reference to Vref level.
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Memory interfaces 6.4.3 DDR3 and DDR3L write cycle Figure 12. DDR3 and DDR3L write cycle Table 32. DDR3 and DDR3L write cycle ID Parameter Symbol CK = 533 MHz Min Max Unit DDR17 DQ and DQM setup time to DQS (differential strobe) tDS 206 — ps DDR18 DQ and DQM hold time to DQS (differential strobe) tDH 280 — ps DDR21 DQS latching rising transitions to associated clock edges tDQSS -0.25 +0.25 tCK (avg) DDR22 DQS high level width tDQSH 0.45 0.
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Memory interfaces 6.4.4 LPDDR2 timing parameter Figure 13. LPDDR2 command and address timing parameter NOTE RESET pin has a external weak pull DOWN requirement if LPDDR2 memory is NOT required to support content retention in the device low power modes where core voltage is off but DRAM voltage is on. NOTE RESET pin has a external weak pull UP requirement if LPDDR2 memory is required to support content retention in the device low power modes where core voltage is off but DRAM voltage is on.
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Memory interfaces NOTE All measurements are in reference to Vref level. NOTE Measurements were done using balanced load and 25 ohms resistor from outputs to VDD_REF. 6.4.5 LPDDR2 read cycle Figure 14. LPDDR2 read cycle Table 34.
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Memory interfaces 6.4.6 LPDDR2 write cycle Figure 15. LPDDR2 write cycle Table 35. LPDDR2 write cycle ID Parameter Symbol CK = 533 MHz Unit Min Max LP17 DQ and DQM setup time to DQS (differential strobe) tDS 280 — ps LP18 DQ and DQM hold time to DQS (differential strobe) tDH 220 — ps LP21 DQS latching rising transitions to associated clock edges tDQSS 0.75 1.25 tCK (avg) LP22 DQS high level width tDQSH 0.4 — tCK (avg) LP23 DQS low level width tDQSL 0.
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Communication modules 6.5 Communication modules 6.5.1 DSPI timing Measurements are with a load of 45 pF on output pins. Input slew = 1 ns, SIUL2_MSCRn[DSE] = 101, and SIUL2_MSCRn[SRE] = 11. NOTE These are not necessarily the default configuration after chip resets. You must ensure the above chip configuration to match the measurements in this section. Table 36. DSPI timing No.
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Communication modules 1. SMPL_PTR should be set to 1. For SPI_CTARn[BR] - 'Baud Rate Scaler' configuration is >= 3. 2. Slave Receive Only Mode can operate at a maximum frequency of 60 MHz. In this mode, the DSPI can receive data on SIN, but no valid data is transmitted on SOUT. 3. This value of 16 ns is with the configuration prescaler values: SPI_CTARn[PCSSCK] - "PCS to SCK Delay Prescaler" configuration is "3" (01h) and SPI_CTARn[CSSCK] - "PCS to SCK Delay Scaler" configuration is "2" (0000h). 4.
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Communication modules PCSx SCK Output (CPOL=0) 10 SCK Output (CPOL =1) 9 Data First Data SIN Last Data 12 SOUT First Data 11 Data Last Data Figure 17. DSPI classic SPI timing — master, CPHA = 1 3 2 SS 1 4 SCK Input (CPOL=0) 4 SCK Input (CPOL=1) 5 SOUT First Data 9 SIN 12 11 Data Last Data Data Last Data 6 10 First Data Figure 18. DSPI classic SPI timing — slave, CPHA = 0 S32V234 Data Sheet, Rev.
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Communication modules SS SCK Input (CPOL=0) SCK Input (CPOL=1) 11 5 6 12 SOUT First Data 9 SIN Data Last Data Data Last Data 10 First Data Figure 19. DSPI classic SPI timing — slave, CPHA = 1 3 PCSx 4 1 2 SCK Output (CPOL=0) 4 SCK Output (CPOL=1) 9 SIN First Data 10 12 SOUT First Data Last Data Data 11 Data Last Data Figure 20. DSPI modified transfer format timing — master, CPHA = 0 S32V234 Data Sheet, Rev.
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Communication modules PCSx SCK Output (CPOL=0) SCK Output (CPOL=1) 10 9 SIN First Data Data 12 First Data SOUT Data Last Data 11 Last Data Figure 21. DSPI modified transfer format timing — master, CPHA = 1 7 8 PCSS PCSx Figure 22. DSPI PCS strobe (PCSS) timing 6.5.2 Ultra High Speed SD/SDIO/MMC Host Interface (uSDHC) Booting from eMMC must be at voltage of 3.3 V. The operation at 1.8 V is possible only during run-time, that is after the boot has completed.
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Communication modules 6.5.2.1 SDR mode timing specifications Figure 23. SDR CMD-DATx Read Timing Figure 24. SDR CMD-DATx Write Timing Table 37.
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Communication modules Table 37. SDR mode timing specification (continued) ID Parameter Symbols Min Max Unit SD3 CLK to Data/CMD Valid tDVO — 3.2 ns SD4 CLK to Data/CMD Invalid tHO -6.3 — ns eSDHC Input/Card Outputs CMD, DAT (Reference to CLK) SD5 DATA/CMD Input Setup time tSUI 4.5 — ns SD6 DATA/CMD Input Hold time tHI 0 — ns 1. In low speed mode, card clock must be lower than 400 kHz, voltage ranges from 2.7 to 3.6 V. 2.
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Communication modules Figure 26. DDR DATA Write timing Figure 27. DDR CMD Read Timing Figure 28. DDR CMD Write Timing S32V234 Data Sheet, Rev.
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Communication modules Table 38. DDR mode timing specification ID Parameter Symbols Min Max Unit Card Input Clock DD1 Clock Frequency (eMMC4.4 DDR) fPP 0 52 MHz DD1 Clock Frequency (SD3.0 DDR) fPP 0 50 MHz DD2 Clock Duty Cycle tDC 45 55 % uSDHC Output/Card Inputs CMD, DAT (Reference to CLK) DD3 CLK to Data Valid tDVO — 6.2 ns DD4 CLK to Data Invalid tHO 2.5 — ns DD5 CLK to CMD Valid tDVO — 3.25 ns DD6 CLK to CMD Invalid tHO –6.
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LFAST electrical characteristics 6.5.3 LFAST electrical characteristics 6.5.3.1 LFAST interface timing diagrams Figure 29. LFAST timing definition S32V234 Data Sheet, Rev.
PAGE 49
LFAST electrical characteristics VIH Differential TX Data Lines 90% 10% pad_p/pad_n VIL Tfall Trise Figure 30. Rise/fall time 6.5.3.2 LFAST Interface electrical characteristics Table 39. LFAST electrical characteristics Symbol Parameter Value1 Conditions Min VDDIO_LFAST Unit Typ Max Operating supply conditions — 1.71 — 1.95 V Data rate — — 312/320 Typ+0.1% Mbps Bias startup time2 — — 0.5 3 µs VOS_DRF Common mode voltage — 1.1 1.2 1.
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FlexRay 7. Total capacitance including silicon, package pin and bond wire 8. Total inductance including silicon, package pin and bond wire 6.5.4 FlexRay 6.5.4.1 FlexRay timing parameters This section provides the FlexRay interface timing characteristics for the input and output signals. These numbers are recommended per the FlexRay Electrical Physical Layer Specification, Version 3.0.1, and subject to change per the final timing analysis of the device. 6.5.4.
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FlexRay PE_Clk TxEN dCCTxEN10 dCCTxEN01 Figure 32. TxEN signal propagation delays 6.5.4.3 TxD TxD dCCTxD50% 80 % 50 % 20 % dCCTxDRISE dCCTxDFALL Figure 33. TxD signal Table 41. TxD output characteristics Name Description1 Min Max Unit dCCTxAsym Asymmetry of sending CC @ 25 pF load (=dCCTxD50% - 100 ns) -2.45 2.45 ns dCCTxDRISE25+dCCTxDFALL25 Sum of Rise and Fall time of TxD signal at the output - 9 ns Table continues on the next page... S32V234 Data Sheet, Rev.
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FlexRay Table 41. TxD output characteristics (continued) Description1 Name Min Max Unit dCCTxD01 Sum of delay between Clk to Q of the last FF and the final output buffer, rising edge - 25 ns dCCTxD10 Sum of delay between Clk to Q of the last FF and the final output buffer, falling edge - 25 ns 1. TxD pin load maximum 25 pF. PE_Clk* TxD dCCTxD10 dCCTxD01 *FlexRay Protocol Engine Clock Figure 34. TxD signal propagation delays 6.5.4.4 RxD Name Table 42.
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Ethernet Controller (ENET) Parameters 6.5.5 Ethernet Controller (ENET) Parameters 6.5.5.1 Ethernet Switching Specifications The following timing specs are defined at the chip I/O pin and must be translated appropriately to arrive at timing specs/constraints for the physical interface. For MII and RMII mode, output load is equal to 25 pF and pad settings are SIUL2_MSCRn[DSE] = 101 and SIUL2_MSCRn[SRE] = 11. For RGMII, output load is 5 pF and pad settings are SIUL2_MSCRn[DSE] = 111 and SIUL2_MSCRn[SRE] = 11.
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Ethernet Controller (ENET) Parameters Figure 35. RMII receive signal timing diagram Figure 36. RMII transmit signal timing diagram 6.5.5.3 Receive and Transmit signal timing specifications for MII interfaces This section provides timing specifications that meet the requirements for MII interfaces for a range of transceiver devices. S32V234 Data Sheet, Rev.
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Ethernet Controller (ENET) Parameters tCYC tPWH RX_CLK (Input) tS tH RXDn, RX_DV, RX_ER (Input) (n = 0-3) Figure 37. MII receive signal timing diagram Table 44.
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Ethernet Controller (ENET) Parameters 6.5.5.4 Receive and Transmit signal timing specifications for RGMII interfaces This section provides timing specs that meet the requirements for RGMII interfaces for a range of transceiver devices. Table 46. Receive signal timing for RGMII interfaces Characteristic Symbol RGMII Mode Min ,1 Clock cycle duration Tcyc ,2 Data to clock output skew at transmitter TskewT Data to clock input skew at receiver TskewR3 3 Typ Unit Max 7.2 — 8.
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Ethernet Controller (ENET) Parameters 6.5.5.5 MII/RMII Serial Management channel timing (MDC/MDIO) Output load is equal to 45 pF and pad settings are SIUL2_MSCRn[DSE] = 101 and SIUL2_MSCRn[SRE] = 11. NOTE These are not necessarily the default configuration after chip resets. You must ensure the above chip configuration to match the measurements in this section. Ethernet works with a maximum frequency of MDC at 2.5 MHz. ENET_MSCR [HOLDTIME] should be set to 010 when Module Clock = 133 MHz.
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Ethernet Controller (ENET) Parameters Table 47. MDIO interface timing specification (continued) ID Parameter Symbols Min Max Unit MDIO Output Timing MDC1 MDC to MDIO Valid tDVO — 50 ns MDC2 MDC to MDIO Invalid tHO 10 — ns MDIO Input Timing MDC3 MDIO Input Setup time tSUI 50 — ns MDC4 MDIO Input Hold time tHI 0 — ns 6.5.6 PCI Express specifications The PCI Express link conforms to the PCI Express Base Specification, Revision 2.1.
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Ethernet Controller (ENET) Parameters 1. See Table 4-9 2.5 and 5.0 GT/s Transmitter Specifications in PCI Express Base Specification for further details. Table 49. PCI Express receiver specifications1 Symbol Parameter 2.5 GT/s 5.0 GT/s Units UI Unit Interval 399.88 (min) 400.12 (max) 199.94 (min) 200.06 (max) ps VRX-DIFF-PP-CC Differential Rx peakpeak voltage for common Refclk Rx architecture 0.175 (min) 1.2 (max) 0.120 (min) 1.2 (max) V TRX-EYE Receiver eye time opening 0.
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Ethernet Controller (ENET) Parameters 2. pg_clk frequency should be greater than 5 MHz for standard mode and 20 MHz for fast mode. Table 51. IIC SCL and SDA output timing specifications Number Symbol Parameter Value Min Unit Max 11 — D Start condition hold time 6 — IP bus cycle2 21 — D Clock low time 10 — IP bus cycle1 33 — D SCL/SDA rise time — 99.6 ns 41 — D Data hold time 7 — IP bus cycle1 51 — D SCL/SDA fall time — 99.
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Display modules 6.6 Display modules 6.6.1 Display Control Unit (2D-ACE) Parameters 6.6.1.1 Interface to TFT panels This section provides the LCD interface timing for a generic active matrix color TFT panel. Measurements are with a load of 20 pF on output pins. Input slew = 1 ns, SIUL2_MSCRn[DSE] = 111, and SIUL2_MSCRn[SRE] = 11. NOTE These are not necessarily the default configuration after chip resets. You must ensure the above chip configuration to match the measurements in this section.
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Display modules VSYNC HSYNC LINE 1 LINE 2 LINE 3 LINE n-1 LINE 4 LINE n HSYNC DE 1 2 3 m-1 m PCLK LD[23:0] Figure 44. TFT LCD interface timing overview 6.6.1.2 Interface to TFT LCD Panels—Pixel Level Timings This section provides the horizontal timing (timing of one line), including both the horizontal sync pulse and data. All parameters shown in the figure below are programmable.
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Display modules Table 52. LCD interface timing parameters—horizontal and vertical (continued) Symbol Characteristic Unit tSH Screen height DELTA_Y * tHSP ns tVSP VSYNC (frame) period (PW_V + BP_V + FP_V + DELTA_Y ) * tHSP ns tHSP tPWH Start of line tBPH tSW tFPH tPCP PCLK Invalid Data LD[23:0] 1 3 2 Invalid Data DELTA_X HSYNC DE Figure 45.
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Display modules Table 53. LCD Interface Timing Parameters—Access Level (continued) Symbol Description Min Max Unit tDV TFT interface VSYNC valid after pixel clock _ 3 ns tDV TFT interface DE valid after pixel clock _ 3 ns tHO TFT interface output hold time for data and control bits 0 _ ns Relative skew between the data bits _ 1.5 ns Figure 47. LCD Interface Timing Parameters—Access Level 6.6.
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Display modules 6.6.3 MIPICSI2 D-PHY electrical and timing parameters The MIPICSI2 D-PHY2 is compliant with MIPICSI2 version 1.0, D-PHY specification Rev. 1.01.00 (for MIPICSI2 sensor port x4 lanes) 6.6.3.1 Electrical and timing Information Table 55.
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Display modules 6.6.3.2 D-PHY signaling levels The signal levels are different for differential HS mode and single-ended LP mode. The figure below shows both the HS and LP signal levels on the left and right sides, respectively. The HS signaling levels are below the LP low-level input threshold such that LP receiver always detects low on HS signals. Table 56.
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Display modules Table 57. D-PHY switching characteristics (continued) Symbol - Parameters Test conditions Maximum serial data rate On DATAP/N inputs.
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Display modules 6.6.3.5 Data to Clock timing Figure 51. Data to Clock timing definition Table 58. Data to Clock timing specifications Symbol Parameters Test conditions Min Typ Max Unit TCLKP Clock Period — 1.33 — 25 ns UIINST UI Instantaneuous — .667 — 12.5 ns TSETUP Data to Clock Setup Time — 0.21 — — UIINST 0.152 — — UIINST 0.21 — — UIINST 0.152 — — UIINST THOLD Clock to Data Hold Time — 1. when D-PHY is supporting maximum data rate > 1 Gbps. 2.
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Debug specifications All materials contained herein are protected by copyright laws, and may not be reproduced, republished, distributed, transmitted, displayed, broadcast or otherwise exploited in any manner without the express prior written permission of MIPI Alliance. MIPI, MIPI Alliance and the dotted rainbow arch and all related trademarks, trade names, and other intellectual property are the exclusive property of MIPI Alliance and cannot be used without its express prior written permission.
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Debug specifications NOTE These are not necessarily the default configuration after chip resets. You must ensure the above chip configuration to match the measurements in this section. Table 59.
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Debug specifications Table 60.
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Debug specifications TCK 4 5 TMS, TDI 6 8 7 TDO Figure 53. JTAG test access port timing TCK 10 JCOMP 9 Figure 54. JTAG JCOMP timing S32V234 Data Sheet, Rev.
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Debug specifications TCK 11 13 Output Signals 12 Output Signals 14 15 Input Signals Figure 55. JTAG boundary scan timing 6.7.2 Debug trace timing specifications Measurements are with a load of 20 pF on output pins. Input slew = 1 ns, SIUL2_MSCRn[DSE] = 111, and SIUL2_MSCRn[SRE] = 11. NOTE These are not necessarily the default configuration after chip resets. You must ensure the above chip configuration to match the measurements in this section. Table 61.
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Debug specifications Table 61. Debug trace operating behaviors (continued) Symbol Description Min. Max. Typical Unit Twh High pulse width 2.8 — 2.95 ns tDV Data output valid — 2.2 1.3 ns tHO Data output hold 0 — 0 ns Figure 56. TRACE_CLKOUT specifications 6.8 Wakeup Unit (WKPU) AC specifications Table 62.
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Thermal attributes Table 64. External interrupt timing (continued) No. Symbol Parameter Conditions Min Max Unit 2 tIPWH IRQ pulse width high - 3 - tCYC 3 tICYC IRQ edge to edge time1 - 6 - tCYC 1. Applies when IRQ pins are configured for rising edge or falling edge events, but not both. IRQ 1 2 3 Figure 57. External interrupt timing 7 Thermal attributes 7.1 Thermal attributes Table 65.
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Dimensions 8 Dimensions 8.1 Obtaining package dimensions Package dimensions are provided in package drawings. To find a package drawing, go to nxp.com and perform a keyword search for the drawing’s document number: Package Body size Pitch NXP document number 621 FC-BGA 17 mm x 17 mm 0.65 mm 98ASA00819D 9 Pinouts 9.1 Package pinouts and signal descriptions For package pinouts and signal descriptions, refer to the Reference Manual.
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Reset sequence Table 66. RESET sequences1 (continued) No. Symbol Parameter TReset Unit Min Typ Max 4 TFRL Functional Reset Sequence Long, Unsecure Boot, BIST disabled 50 — 90 µs 5 TFRS Functional Reset Sequence Short, Unsecure Boot, BIST disabled 2 — 7 µs 1. All the Reset durations assume boot code execution time for Execute-in-place for QuadSPI booting, Unsecure mode with Trimmed FIRC module. Boot code is using execution using PLL and no DCD download is assumed.
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Reset sequence JUMP TO APPLICATION CODE CLOCK INITIALIZATION AND QSPI INIT DCD EXECUTION TO CONFIGURE DDR APPLICATION IMAGE DOWNLOAD 3.47 ms Boot Length 25.3 DDR(FAST BOOT) 1.6 0.82 0.2 CSE FIRMWARE DOWNLOAD + APPLICATION IMAGE AUTHENTICATION (SECURE BOOT) Authentication Length RESET AFTER SELF TEST 7.4 CSE AUTHENTICATION TIME FROM DDR 1.7 0 Time in ms 4 MB 256 kB 128 kB 4.1 5 10 Time in ms 32kB 256 kB 128 kB 32 kB Figure 58. Boot diagram 10.
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Reset sequence driving it low. The reset sequence durations given in Table 66 are applicable only if the internal reset sequence is not prolonged by an external reset generator keeping RESET (Active-low) asserted low beyond the last Phase3.
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Power sequencing requirements Reset Sequence Trigger Reset Sequence Start Condition RESET PHASE1,2 Fuse Init PHASE3 Device Config DRUN Application Boot Ex ecut ion code execution TFRL, min < TRESET < TFRL, max Figure 62. Functional reset sequence long Reset Sequence Trigger Reset Sequence Start Condition RESET PHASE3 DRUN Boot code Application Execution execution TFRS, min < TRESET < TFRS, max Figure 63.
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Revision history • DDR0_VREF0 and DDR1_VREF0 supplies are expected to be 0.5 of VDD_DDR0_IO and VDD_DDR1_IO supplies and are to track VDD_HV_DDR0 and VDD_HV_DDR1 supply variations as measured at the receiver. Peak-to-Peak noise on DDR0_VREF0 and DDR1_VREF0 supplies should be between +/- 15 mV. • The maximum rise time for the POR and RESET signal is 1 ms.
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Revision history Table 69. Revision history (continued) Revision Date 2 06/2015 Description of changes Overall: • Editorial changes. Added topic PCB routing guideliness. Added topic RESET pin glitch filter specifications. In Table 16, added the sentence "For internal ADC channels, the minimum sampling time required is 3 microsecond" in the foot note on "Sample time". In Power Management Controller (PMC) electrical specifications, changed the introductory paragraph.
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Revision history Table 69. Revision history (continued) Revision Date Description of changes In Table 59, updated minimum value of TCK Cycle Time and the footnote. Also, added CJTAG TCK Cycle Time and updated maximum value of TCK Rise and Fall Times. Added DDR3L mode and DDR3L mode DC electrical specifications. Removed LPDDR2 I/O AC specifications. Deleted the word "Dual" from "Dual QuadSPI supporting Execute-In-Place (XIP)" in "Features" section as there is only one QuadSPI.
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Revision history Table 69. Revision history Revision Date Description of changes • • • • • • • • • use cases are removed, and PCIE_VPH (5 GHz operation) use case has been changed from 30 to 32 mA. Max values of both PCIE_VP and PCIE_VPH (for both cases) have been included. • modified the table heading. Removed Front Camera (w power binning) from VDD_LV_CORE and updated max values for “Adder 4x A53 CPU with Dhrystone MIPS running on each CPU @1 GHz” from 1.0 A to 1.4 A.
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Revision history Table 69. Revision history Revision Date Description of changes • In Table 22 : • unit for Total Jitter has been changed from ps to ns. • removed max Deterministic and max Random jitter specifications; added footnote in max Total Jitter. • In Table 23 : • Made modification in DDR mode. • Updated values of QuadSPI_SOCCR[FDCC_FB] and QuadSPI_SOCCR[FDCC_FA] for SDR and DDR mode (internal DQS Mode) and added footnote “Device qualification is not complete.
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Revision history Table 69. Revision history Revision Date Description of changes • • • • • • • • • • • • • • • • • • • • • • • • • • • Updated the footnote in minimum and maximum values of “Common mode voltage” (Receiver). • Changed minimum value of “Differential input voltage” (Receiver) from 100 to 150 mV. In Table 44 changed minimum and maximum value of RX_CLK duty cycle. In Table 45 : • changed minimum and maximum value of TX_CLK duty cycle and minimum value of Out delay from TX_CLK.
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Revision history Table 69. Revision history (continued) Revision Date Description of changes • In Thermal Monitoring Unit (TMU), changed all occurrences of “Temperature Sensor” to “Thermal Monitoring Unit”. • In 48 MHz FIRC electrical characteristics, min and max value of “IRCOSC frequency variation with respect to supply and temperature after process trimming” has been changed from -5 to -10 and +5 to +10 %.
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Revision history Table 69. Revision history (continued) Revision Date Description of changes • In PCB routing guidelines, added a note under the "CLK/Addess/Commands" section. And updated the third point under the section for clarification. • In Table 4, row 2 and 3 has been split into sub-sections for different I/O voltages. • In Table 6, updated max value for VDD_HV_LFASTPLL when "PLL operating with 320 MHz (LFAST used)". Value is changed from 24 mA to 26 mA.
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Revision history Table 69. Revision history (continued) Revision Date Description of changes • JTAG interface timing • Debug trace timing specifications • Electrostatic discharge (ESD) specifications - Removed the VESD(CDM) specs for corner pins. 7 08/2018 • GPIO speed at various voltage levels - Added the text "The maximum rise time for all GPIO pins is 1 ms" to the existing note. • Power sequencing requirements - Updated the last bullet to "The maximum rise time for the POR and RESET.........
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