Datasheet

Table 57. Revision history (continued)
Revision Date Description of changes
12 08/2018 In Table 12 of PLL electrical specifications, changed text of footnote 1:
•
from: "f
PLL0IN
frequency must be scaled down using PLLDIG_PLL0DV[PREDIV] to ensure
PFD input signal is in the range 8 MHz to 20 MHz."
• to: "Ensure that the f
PLL0IN
frequency divided by PLLDIG_PLL0DV[PREDIV] is in the range 8
MHz to 20 MHz."
In Table 17 of Enhanced Queued Analog-to-Digital Converter (eQADC), added footnote about Max
value of Conversion Cycles (CC): "128 sampling cycles (LST=128), differential conversion, pregain
of x4"
In Table 38 of External Bus Interface (EBI) timing, changed text of footnote 1:
• from: "EBI timing specified at V
DD
= 1.08 V to 1.32 V, V
DDE
= 3.0 V to 3.6 V, T
A
= T
L
to T
H
,
and C
L
= 30 pF with SIU_PCR[DSC] = 10b for ADDR/CTRL and SIU_PCR[DSC] = 11b for
CLKOUT/DATA."
• to: "EBI timing specified at V
DD
= 1.08 V to 1.32 V, V
DDE
= 3.0 V to 3.6 V, T
A
= T
L
to T
H
, and
C
L
= 30 pF with SIU_PCR[DSC] = 11b for ADDR/CTRL and SIU_PCR[SRC] = 11b for DATA/
ALE."
In I/O pad current specifications added the text "The EBI power segments have..........segment does
not exceed the spec".
Document revision history
MPC5777C Microcontroller Data Sheet Data Sheet, Rev. 13, 08/2018.
NXP Semiconductors 89