Datasheet
RX_CLK (input)
RXD[3:0] (inputs)
RX_DV
M1
M2
M4
M3
Figure 41. MII receive signal timing diagram
3.13.10.2 MII transmit signal timing (TXD[3:0], TX_EN, and TX_CLK)
The transmitter functions correctly up to a TX_CLK maximum frequency of 25 MHz
+1%. There is no minimum frequency requirement. The system clock frequency must be
at least equal to or greater than the TX_CLK frequency.
The transmit outputs (TXD[3:0], TX_EN) can be programmed to transition from either
the rising or falling edge of TX_CLK, and the timing is the same in either case. This
options allows the use of noncompliant MII PHYs.
Refer to the MPC5777C Microcontroller Reference Manual's Fast Ethernet Controller
(FEC) chapter for details of this option and how to enable it.
Table 49. MII transmit signal timing
1
Symbol Characteristic
Value
2
Unit
Min Max
M5 TX_CLK to TXD[3:0], TX_EN invalid 4.5 — ns
M6 TX_CLK to TXD[3:0], TX_EN valid — 25 ns
M7 TX_CLK pulse width high 35% 65% TX_CLK period
M8 TX_CLK pulse width low 35% 65% TX_CLK period
1. All timing specifications valid to the pad input levels defined in I/O pad specifications.
2. Output parameters are valid for C
L
= 25 pF, where C
L
is the external load to the device. The internal package capacitance
is accounted for, and does not need to be subtracted from the 25 pF value.
Electrical characteristics
MPC5777C Microcontroller Data Sheet Data Sheet, Rev. 13, 08/2018.
NXP Semiconductors 79