Datasheet
Table 47. DSPI CMOS master timing – output only – timed serial bus mode TSB = 1 or ITSB
= 1, CPOL = 0 or 1, continuous SCK clock
1, 2
(continued)
# Symbol Characteristic
Condition
3
Value
4
Unit
Pad drive
5
Load (C
L
) Min Max
3 t
CSH
PCS hold after SCK
6
PCR[SRC]=11b PCS: 0 pF
SCK: 50 pF
–14 — ns
PCR[SRC]=10b PCS: 0 pF
SCK: 50 pF
–14 — ns
PCR[SRC]=01b PCS: 0 pF
SCK: 50 pF
–33 — ns
PCS: PCR[SRC]=01b
SCK: PCR[SRC]=10b
PCS: 0 pF
SCK: 50 pF
–35 — ns
4 t
SDC
SCK duty cycle
7
PCR[SRC]=11b 0 pF 1/2t
SCK
– 2 1/2t
SCK
+ 2 ns
PCR[SRC]=10b 0 pF 1/2t
SCK
– 2 1/2t
SCK
+ 2 ns
PCR[SRC]=01b 0 pF 1/2t
SCK
– 5 1/2t
SCK
+ 5 ns
SOUT data valid time (after SCK edge)
9 t
SUO
SOUT data valid time
from SCK
CPHA = 1
8
PCR[SRC]=11b 25 pF — 7.0 ns
PCR[SRC]=10b 50 pF — 8.0 ns
PCR[SRC]=01b 50 pF — 18.0 ns
SOUT data hold time (after SCK edge)
10 t
HO
SOUT data hold time
after SCK
CPHA = 1
8
PCR[SRC]=11b 25 pF –9.0 — ns
PCR[SRC]=10b 50 pF –10.0 — ns
PCR[SRC]=01b 50 pF –21.0 — ns
1. TSB = 1 or ITSB = 1 automatically selects MTFE = 1 and CPHA = 1.
2. All output timing is worst case and includes the mismatching of rise and fall times of the output pads.
3. When a characteristic involves two signals, the pad drive and load conditions apply to each signal's pad, unless specified
otherwise.
4. All timing values for output signals in this table are measured to 50% of the output voltage.
5. Pad drive is defined as the PCR[SRC] field setting in the SIU. Timing is guaranteed to same drive capabilities for all
signals; mixing of pad drives may reduce operating speeds and may cause incorrect operation.
6. With TSB mode or Continuous SCK clock mode selected, PCS and SCK are driven by the same edge of DSPI_CLKn. This
timing value is due to pad delays and signal propagation delays.
7. t
SDC
is only valid for even divide ratios. For odd divide ratios the fundamental duty cycle is not 50:50. For these odd divide
ratios cases, the absolute spec number is applied as jitter/uncertainty to the nominal high time and low time.
8. SOUT Data Valid and Data hold are independent of load capacitance if SCK and SOUT load capacitances are the same
value.
Electrical characteristics
MPC5777C Microcontroller Data Sheet Data Sheet, Rev. 13, 08/2018.
NXP Semiconductors 77