Datasheet

Table 44. DSPI CMOS master modified timing (full duplex and output only) – MTFE = 1,
CPHA = 0 or 1
1
(continued)
# Symbol Characteristic
Condition
2
Value
3
Unit
Pad drive
4
Load (C
L
) Min Max
3 t
ASC
After SCK delay PCR[SRC]=11b PCS: 0 pF
SCK: 50 pF
(M
7
× t
SYS
, 6
) – 35 — ns
PCR[SRC]=10b PCS: 0 pF
SCK: 50 pF
(M
7
× t
SYS
, 6
) – 35 —
PCR[SRC]=01b PCS: 0 pF
SCK: 50 pF
(M
7
× t
SYS
, 6
) – 35 —
PCS: PCR[SRC]=01b
SCK: PCR[SRC]=10b
PCS: 0 pF
SCK: 50 pF
(M
7
× t
SYS
, 6
) – 35 —
4 t
SDC
SCK duty cycle
8
PCR[SRC]=11b 0 pF 1/2t
SCK
– 2 1/2t
SCK
+ 2 ns
PCR[SRC]=10b 0 pF 1/2t
SCK
– 2 1/2t
SCK
+ 2
PCR[SRC]=01b 0 pF 1/2t
SCK
– 5 1/2t
SCK
+ 5
PCS strobe timing
5 t
PCSC
PCSx to PCSS
time
9
PCR[SRC]=10b 25 pF 13.0 — ns
6 t
PASC
PCSS to PCSx
time
9
PCR[SRC]=10b 25 pF 13.0 — ns
SIN setup time
7 t
SUI
SIN setup time to
SCK
CPHA = 0
10
PCR[SRC]=11b 25 pF 29 – (P
11
× t
SYS
, 6
) — ns
PCR[SRC]=10b 50 pF 31 – (P
11
× t
SYS
, 6
) —
PCR[SRC]=01b 50 pF 62 – (P
11
× t
SYS
, 6
) —
SIN setup time to
SCK
CPHA = 1
10
PCR[SRC]=11b 25 pF 29.0 — ns
PCR[SRC]=10b 50 pF 31.0 —
PCR[SRC]=01b 50 pF 62.0 —
SIN hold time
8 t
HI
12
SIN hold time from
SCK
CPHA = 0
10
PCR[SRC]=11b 0 pF –1 + (P
11
× t
SYS
, 6
) — ns
PCR[SRC]=10b 0 pF –1 + (P
11
× t
SYS
, 6
) —
PCR[SRC]=01b 0 pF –1 + (P
11
× t
SYS
, 6
) —
SIN hold time from
SCK
CPHA = 1
10
PCR[SRC]=11b 0 pF –1.0 — ns
PCR[SRC]=10b 0 pF –1.0 —
PCR[SRC]=01b 0 pF –1.0 —
SOUT data valid time (after SCK edge)
9 t
SUO
SOUT data valid
time from SCK
CPHA = 0
13
PCR[SRC]=11b 25 pF — 7.0 + t
SYS
6
ns
PCR[SRC]=10b 50 pF — 8.0 + t
SYS
6
PCR[SRC]=01b 50 pF — 18.0 + t
SYS
6
SOUT data valid
time from SCK
CPHA = 1
13
PCR[SRC]=11b 25 pF — 7.0 ns
PCR[SRC]=10b 50 pF — 8.0
PCR[SRC]=01b 50 pF — 18.0
SOUT data hold time (after SCK edge)
Table continues on the next page...
Electrical characteristics
MPC5777C Microcontroller Data Sheet Data Sheet, Rev. 13, 08/2018.
70 NXP Semiconductors