Datasheet

PCSx
SCK Output
(CPOL = 0)
SCK Output
(CPOL = 1)
SIN
SOUT
First Data
First Data
Data
Data
Last Data
Last Data
t
SUI
t
HI
t
SUO
t
HO
Figure 33. DSPI CMOS master mode – classic timing, CPHA = 1
PCSS
PCSx
tPCSC
tPASC
Figure 34. DSPI PCS strobe (PCSS) timing (master mode)
3.13.9.1.2 DSPI CMOS Master Mode – Modified Timing
Table 44. DSPI CMOS master modified timing (full duplex and output only) –
MTFE = 1, CPHA = 0 or 1
1
# Symbol Characteristic
Condition
2
Value
3
Unit
Pad drive
4
Load (C
L
) Min Max
1 t
SCK
SCK cycle time PCR[SRC]=11b 25 pF 33.0 — ns
PCR[SRC]=10b 50 pF 80.0 —
PCR[SRC]=01b 50 pF 200.0 —
2 t
CSC
PCS to SCK delay PCR[SRC]=11b 25 pF (N
5
× t
SYS
, 6
) – 16 — ns
PCR[SRC]=10b 50 pF (N
5
× t
SYS
, 6
) – 16 —
PCR[SRC]=01b 50 pF (N
5
× t
SYS
, 6
) – 18 —
PCS: PCR[SRC]=01b
SCK: PCR[SRC]=10b
50 pF (N
5
× t
SYS
, 6
) – 45 —
Table continues on the next page...
Electrical characteristics
MPC5777C Microcontroller Data Sheet Data Sheet, Rev. 13, 08/2018.
NXP Semiconductors 69