Datasheet
3.12.2 Flash memory Array Integrity and Margin Read specifications
Table 31. Flash memory Array Integrity and Margin Read specifications
Symbol Characteristic Min Typical Max
1
Units
2
t
ai16kseq
Array Integrity time for sequential sequence on 16 KB block. — — 512 x
Tperiod x
Nread
—
t
ai32kseq
Array Integrity time for sequential sequence on 32 KB block. — — 1024 x
Tperiod x
Nread
—
t
ai64kseq
Array Integrity time for sequential sequence on 64 KB block. — — 2048 x
Tperiod x
Nread
—
tai256kseq
Array Integrity time for sequential sequence on 256 KB block. — — 8192 x
Tperiod x
Nread
—
t
mr16kseq
Margin Read time for sequential sequence on 16 KB block. 73.81 — 110.7 μs
t
mr32kseq
Margin Read time for sequential sequence on 32 KB block. 128.43 — 192.6 μs
t
mr64kseq
Margin Read time for sequential sequence on 64 KB block. 237.65 — 356.5 μs
t
mr256kseq
Margin Read time for sequential sequence on 256 KB block. 893.01 — 1,339.5 μs
1. Array Integrity times need to be calculated and is dependent on system frequency and number of clocks per read. The
equation presented require Tperiod (which is the unit accurate period, thus for 200 MHz, Tperiod would equal 5e-9) and
Nread (which is the number of clocks required for read, including pipeline contribution. Thus for a read setup that requires
6 clocks to read with no pipeline, Nread would equal 6. For a read setup that requires 6 clocks to read, and has the
address pipeline set to 2, Nread would equal 4 (or 6 - 2).)
2. The units for Array Integrity are determined by the period of the system clock. If unit accurate period is used in the
equation, the results of the equation are also unit accurate.
3.12.3 Flash memory module life specifications
Table 32. Flash memory module life specifications
Symbol Characteristic Conditions Min Typical Units
Array P/E
cycles
Number of program/erase cycles per block
for 16 KB, 32 KB and 64 KB blocks.
1
— 250,000 — P/E
cycles
Number of program/erase cycles per block
for 256 KB blocks.
2
— 1,000 250,000 P/E
cycles
Data
retention
Minimum data retention. Blocks with 0 - 1,000 P/E
cycles.
50 — Years
Blocks with 100,000 P/E
cycles.
20 — Years
Blocks with 250,000 P/E
cycles.
10 — Years
1. Program and erase supported across standard temperature specs.
2. Program and erase supported across standard temperature specs.
Electrical characteristics
MPC5777C Microcontroller Data Sheet Data Sheet, Rev. 13, 08/2018.
NXP Semiconductors 49