Datasheet

3.10.1 LFAST interface timing diagrams
Signal excursions above this level NOT allowed
Max. common mode input at RX
1743 mV
1600 mV
|Vo D|
Max Differential Voltage =
285 mV p-p (LFAST)
400 mV p-p (MSC/DSPI)
Minimum Data Bit Time
Opening =
0.55 * T (LFAST)
0.50 * T (MSC/DSPI)
|Vo D|
Min Differential Voltage =
100 mV p-p (LFAST)
150 mV p-p (MSC/DSPI)
“No-Go” Area
|PER
EYE
Data Bit Period
T = 1 /F
DATA
Min. common mode input at RX
Signal excursions below this level NOT allowed
0 V
150 mV
V
OS =
1.2 V +/- 10%
TX common mode
V
ICOM
|PER
EYE
Figure 8. LFAST and MSC/DSPI LVDS timing definition
Electrical characteristics
MPC5777C Microcontroller Data Sheet Data Sheet, Rev. 13, 08/2018.
NXP Semiconductors 35