Datasheet

Features
MPC5566 Microcontroller Product Brief, Rev. 1
Freescale Semiconductor 9
2.6.8 System Integration Unit (SIU)
• Centralized GPIO control of bus pins:
— 416 BGA package: 178 pins
— 496 CSP BGA package: 225 pins
• Centralized pad control on a per-pin basis
• System reset monitoring and generation
• External interrupt inputs, filtering and control
• Internal multiplexer submodule
2.6.9 Error Correction Status Module (ECSM)
Configurable error-correcting codes (ECC) reporting for internal SRAM and flash memories.
2.6.10 On-chip Flash Memory
• 3 MB burst flash memory
• 384 K × 64-bit configuration
• Censorship protection scheme to prevent flash content visibility
• Hardware read-while-write feature that allows blocks to be erased/programmed while other blocks
are being read (used for EEPROM emulation and data calibration)
• 28 blocks with sizes ranging from 16 – 128 Kbyte to support features such as boot block, operating
system block, and EEPROM emulation. Blocks are structured as follows:
— 2 x 16 Kbyte
— 2 x 48 Kbyte
— 2 x 64 Kbyte
— 22 x 128 Kbyte
• Read while write with multiple partitions
• Parallel programming mode to support rapid end-of-line programming
• Hardware programming state machine
2.6.11 Configurable Cache Memory, 0 – 32 Kbytes
• Four-way and eight-way set-associative unified (instruction and data) cache
• Decouples processor performance from system memory performance
2.6.12 On-chip Internal Static RAM (SRAM)
• Total of 128 Kbyte internal general-purpose static RAM (SRAM), of which 32 Kbyte are
designated to standby power
• ECC performs single-bit correction and double-bit error detection