Datasheet

Features
MPC5566 Microcontroller Product Brief, Rev. 1
Freescale Semiconductor 7
2.6.2 System Bus Crossbar Switch (XBAR)
• Four master ports and five slave ports
• 32-bit address bus and 64-bit data bus
• Simultaneous accesses from different masters to different slaves (there is no clock penalty when a
parked master accesses a slave)
2.6.3 Enhanced Direct Memory Access (eDMA) Controller
• 64 channels support independent 8-, 16- and 32-bit single value or block transfers
• Supports variable sized queues and circular queues
• Source and destination address registers are independently configured to post-increment or remain
constant
• Each transfer is initiated by a peripheral, CPU, or eDMA channel request
• Each eDMA channel can optionally send an interrupt request to the CPU on completion of a single
value or block transfer
2.6.4 Interrupt Controller (INTC)
• 332 total interrupt vectors
1
— 298 peripheral interrupt requests
— eight software settable sources
— 26 reserved
• Unique 9-bit vector per interrupt source
• 16 priority levels with fixed hardware arbitration within priority levels for each interrupt source
• Priority elevation for shared resources
2.6.5 Frequency Modulated Phase-locked Loop (FMPLL)
• Input clock frequency 8 to 20 MHz
• Current controlled oscillator (ICO) range from 48 MHz to maximum device frequency
• Reduced frequency divider (RFD) for reduced frequency operation without re-lock
• Four selectable modes of operation
• Programmable frequency modulation
• Lock-detect circuitry continuously monitors lock status
• Loss-of-clock (LOC) detection for reference and feedback clocks
• Self-clocked mode (SCM) operation
• On-chip loop filter (reduces number of external components required)
• Engineering clock output configurable to divide-by-2 to 126 of the system clock frequency
1. Although this device has a maximum of 329 interrupts, the logic requires that the total number of interrupts be divisible by four.
Therefore, the total number of interrupts specified for this device is 332.