Datasheet

MPC5566 Microcontroller Product Brief, Rev. 1
Features
Freescale Semiconductor6
2.6 Module Features
The following is a brief summary of the functional blocks in the MPC5566. For more detailed information,
refer to the MPC5566 Reference Manual (MPC5566RM).
2.6.1 High Performance e200z6 Core Processor
• 32-bit PowerPC Book E compliant CPU
• Freescale Variable Length Encoding (VLE) enhancements for code size footprint reduction
• Thirty-two 64-bit general-purpose registers (GPRs)
• Memory management unit (MMU) with 32-entry fully-associative translation look-aside buffer
(TLB)
• Branch processing unit
• Fully pipelined load/store unit
• 32-Kbyte unified cache with line locking
— Four-way and eight-way set associative
— Two 32-bit fetches per clock
— Eight-entry store buffer
— Way locking
— Supports assigning cache as instruction or data only on a per way basis
— Supports tag and data parity
• Vectored interrupt support
• Interrupt latency less than 70 ns @ 144 MHz (measured from interrupt request to execution of first
instruction of interrupt exception handler)
• Reservation instructions for implementing read-modify-write constructs (internal SRAM and
flash)
• Signal processing engine (SPE) auxiliary processing unit (APU) operating on 64-bit general
purpose registers
• Floating point
—IEEE® 754 compatible with software wrapper
— Single-precision hardware, double-precision software library
— Conversion instructions between single-precision floating point and fixed point
• Long cycle time instructions, except for guarded loads, do not increase interrupt latency in the
MPC5566. To reduce latency, long cycle-time instructions are aborted upon interrupt requests.
• Extensive system development support through Nexus debug module