Datasheet

Features
MPC5566 Microcontroller Product Brief, Rev. 1
Freescale Semiconductor 5
2.3 Operating Parameters
• Fully static operation, up to 144 MHz
• –40° to 150° C junction temperature
• 1.5 V core, 3.0 – 5.5 V I/O, 1.6 – 3.6 V external bus, 2.5 – 3.6 V Nexus pins
2.4 Package
A 416-pin ball grid array (BGA)
2.5 Chip-level Features
• Low-power design
— Less than 1.2 Watts power dissipation
— Designed for dynamic power management of core and peripherals
— Software-controlled clock gating of peripherals
— Separate power supply for stand-by operation for portion of internal SRAM
• Fabricated in 0.13 μm process
• Single-issue, 32-bit Book E compliant Power Architecture technology e200z6 CPU core
• 64-channel enhanced direct memory access controller (eDMA)
• Interrupt controller (INTC) capable of handling 329 selectable-priority interrupt sources
• Frequency modulated phase-locked loop (FMPLL)
• External bus interface (EBI)
• Error correction status module (ECSM)
• System integration unit (SIU)
• 3 MB on-chip flash with flash bus interface unit (FBIU)
• 128-Kbyte on-chip static RAM
• Boot assist module (BAM)
• Support for dynamic calibration with four calibration chip-selects
• 24-channel enhanced modular I/O system (eMIOS)
• Dual enhanced time processor unit (eTPU) engines; each eTPU engine controls 32 hardware
channels, for a total of 64 hardware channels
• Two enhanced queued analog-to-digital converter (eQADC) modules
• Four deserial serial peripheral interface (DSPI) modules
• Two enhanced serial communication interface (eSCI) modules
• Four controller area network (FlexCAN) modules
• Nexus development interface (NDI) per IEEE-ISTO 5001-2003 standard
• Device/board test support per Joint Test Action Group (JTAG) of IEEE