Datasheet

MPC5566 Microcontroller Product Brief, Rev. 1

Features

Freescale Semiconductor12

• Programmable clock source: system clock or oscillator clock

• Reception queue model; set more than one receive message buffer with the same ID

• Backwards compatibility with previous FlexCAN modules

2.6.20 Nexus Development interface (NDI)

• Per IEEE®-ISTO 5001-2003

• Real time development support for PowerPC core and eTPU engines through Nexus Class 3

(some Class 4 support)

• Data trace of eDMA accesses

• Read and write access

• Configured via the IEEE® 1149.1 (JTAG) port

• High bandwidth mode for fast message transmission

• Reduced bandwidth mode for reduced pin usage

2.6.21 IEEE® 1149.1 JTAG Controller (JTAGC)

•IEEE® 1149.1-2001 Test Access Port (TAP) interface

• JCOMP input that provides the ability to share the TAP. Selectable modes of operation include

JTAGC/debug or normal system operation.

• Five-bit instruction register that supports IEEE® 1149.1-2001 defined instructions

• Five-bit instruction register that supports additional public instructions

• Three test data registers: a bypass register, a boundary scan register, and a device identification

• TAP controller state machine that controls the operation of the data registers, instruction register

and associated circuitry

2.6.22 Voltage Regulator Controller

Provides a low cost solution to power the core logic. It reduces the number of power supplies required from

the customer power supply chip.

2.6.23 Power-on Reset (POR) Block

Provides initial reset condition up to the voltage at which pins (RESET) can be read safely. It does not

guarantee the safe operation of the chip at specified minimum operating voltages.

2.6.24 Fast Ethernet Controller (FEC)

•IEEE® 802.3 MAC (compliant with IEEE® 802.3 1998 edition)

• Built-in FIFO and DMA controller