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Freescale Semiconductor

Product Brief

Document Number: MPC5566PB

Rev. 1, 12/2007

Contents

Designed for engine management and high-temperature

industrial applications, the MPC5566 32-bit embedded

controller is part of Freescale Semiconductor’s

MPC5500 family that uses the Book E compliant Power

Architecture™ technology core with variable length

encoding (VLE). The core complies with the Power

Architecture embedded category, and is 100 percent

user-mode compatible with the original PowerPC™ user

instruction set architecture (UISA). It offers system

performance up to five times that of its MPC500

predecessors, bringing you the reliability and familiarity

of the proven Power Architecture technology.

A comprehensive suite of hardware and software

development tools are available to help simplify and

speed system design. Development support is available

from leading tools vendors providing compilers,

debuggers and simulation development environments.

This document provides an overview of the MPC5566

microcontroller features, including the major functional

components.

1 Applications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

2.1 MPC5500 Device Comparison . . . . . . . . . . . . . . . . 2

2.2 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

2.3 Operating Parameters . . . . . . . . . . . . . . . . . . . . . . . 5

2.4 Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

2.5 Chip-level Features . . . . . . . . . . . . . . . . . . . . . . . . . 5

2.6 Module Features . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

3 Developer Environment. . . . . . . . . . . . . . . . . . . . . . . . . . 13

MPC5566 Microcontroller Product

Brief

Summary of content (14 pages)

PAGE 1
Freescale Semiconductor Product Brief Document Number: MPC5566PB Rev. 1, 12/2007 MPC5566 Microcontroller Product Brief Designed for engine management and high-temperature industrial applications, the MPC5566 32-bit embedded controller is part of Freescale Semiconductor’s MPC5500 family that uses the Book E compliant Power Architecture™ technology core with variable length encoding (VLE).
PAGE 2
Applications 1 Applications The MPC5500 is well suited to network-connected automotive and industrial applications that require complex real-time control.
PAGE 3
Features Table 1. MPC5554 vs.
PAGE 4
Features 2.2 Block Diagram Figure 1 shows a top-level block diagram of the MPC5566.
PAGE 5
Features 2.3 • • • 2.4 Operating Parameters Fully static operation, up to 144 MHz –40° to 150° C junction temperature 1.5 V core, 3.0 – 5.5 V I/O, 1.6 – 3.6 V external bus, 2.5 – 3.6 V Nexus pins Package A 416-pin ball grid array (BGA) 2.5 • • • • • • • • • • • • • • • • • • • • • Chip-level Features Low-power design — Less than 1.
PAGE 6
Features 2.6 Module Features The following is a brief summary of the functional blocks in the MPC5566. For more detailed information, refer to the MPC5566 Reference Manual (MPC5566RM). 2.6.
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Features 2.6.2 • • • 2.6.3 • • • • • 2.6.4 • • • • 2.6.
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Features 2.6.6 • • • • • • • • • • • • • • 2.6.7 • • • • • • • External Bus Interface (EBI) 1.8 – 3.3 V I/O nominal voltage Memory controller with support for various memory types MPC5566 specifications: — 416 BGA: 32-bit data bus, 26-bit address bus — 496 BGA: 32-bit data bus, 26-bit address bus 26-bit address bus: the two most significant bits (MSBs), ADDR[6:7], are multiplexed with the two least significant bits (LSBs) ADDR[30:31].
PAGE 9
Features 2.6.8 • • • • • System Integration Unit (SIU) Centralized GPIO control of bus pins: — 416 BGA package: 178 pins — 496 CSP BGA package: 225 pins Centralized pad control on a per-pin basis System reset monitoring and generation External interrupt inputs, filtering and control Internal multiplexer submodule 2.6.9 Error Correction Status Module (ECSM) Configurable error-correcting codes (ECC) reporting for internal SRAM and flash memories. 2.6.
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Features 2.6.13 Boot Assist Module (BAM) Enables and manages the transition of the MCU from reset to user-code execution in the following configurations: • User application can boot from internal or external flash memory • Download and execute program code via FlexCAN or eSCI • User application can boot to classic Power PC code or VLE code 2.6.
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Features • • DMA and interrupt request support Supports all functional modes from MPC5xx family QADC module 2.6.
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Features • • • Programmable clock source: system clock or oscillator clock Reception queue model; set more than one receive message buffer with the same ID Backwards compatibility with previous FlexCAN modules 2.6.20 • • • • • • • Per IEEE®-ISTO 5001-2003 Real time development support for PowerPC core and eTPU engines through Nexus Class 3 (some Class 4 support) Data trace of eDMA accesses Read and write access Configured via the IEEE® 1149.
PAGE 13
Developer Environment • • • • • • • • • • • • 3 Fully software compatible with the FEC module of Freescale's industry standard PowerQUICC communications controller Full compliance with the IEEE 802.3 standard for 10/100 base-T Support for different Ethernet physical interfaces: IEEE® 802.
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How to Reach Us: Home Page: www.freescale.com E-mail: support@freescale.com USA/Europe or Locations Not Listed: Freescale Semiconductor Technical Information Center, CH370 1300 N. Alma School Road Chandler, Arizona 85224 +1-800-521-6274 or +1-480-768-2130 support@freescale.