Datasheet

Modules list
i.MX RT1015 Crossover Processors Data Sheet for Consumer Products, Rev. 0.1, 03/2019
NXP Semiconductors 7
3 Modules list
The i.MX RT1015 processors contain a variety of digital and analog modules. Table 2 describes these
modules in alphabetical order.
Table 2. i.MX RT1015 modules list
Block mnemonic Block name Subsystem Brief description
ADC1 Analog to Digital
Converter
Analog The ADC is a 12-bit general purpose analog to digital
converter.
AOI And-Or-Inverter Cross Trigger The AOI provides a universal boolean function
generator using a four team sum of products expression
with each product term containing true or complement
values of the four selected inputs (A, B, C, D).
Arm Arm Platform Arm The Arm Core Platform includes 1x Cortex-M7 core. It
also includes associated sub-blocks, such as Nested
Vectored Interrupt Controller (NVIC), Floating-Point
Unit (FPU), Memory Protection Unit (MPU), and
CoreSight debug modules.
BEE Bus Encryption Engine Security On-The-Fly FlexSPI Flash Decryption
CCM
GPC
SRC
Clock Control Module,
General Power
Controller, System Reset
Controller
Clocks, Resets, and
Power Control
These modules are responsible for clock and reset
distribution in the system, and also for the system
power management.
CSU Central Security Unit Security The Central Security Unit (CSU) is responsible for
setting comprehensive security policy within the i.MX
RT1015 platform.
DAP Debug Access Port System Control
Peripherals
The DAP provides real-time access for the debugger
without halting the core to:
• System memory and peripheral registers
• All debug configuration registers
The DAP also provides debugger access to JTAG scan
chains. The DAP module is internal to the Cortex-M7
Core Platform.
DCDC DCDC Converter Analog The DCDC module is used for generating power supply
for core logic. Main features are:
• Adjustable high efficiency regulator
• Supports 3.3 V input voltage
• Supports nominal run and low power standby modes
• Supports at 0.9 ~ 1.3 V output in run mode
• Supports at 0.9 ~ 1.0 V output in standby mode
• Over current and over voltage detection
eDMA enhanced Direct Memory
Access
System Control
Peripherals
There is an enhanced DMA (eDMA) engine and two
DMA_MUX.
• The eDMA is a 32 channel DMA engine, which is
capable of performing complex data transfers with
minimal intervention from a host processor.
• The DMA_MUX is capable of multiplexing up to 128
DMA request sources to the 32 DMA channels of
eDMA.