Datasheet

i.MX RT1015 Crossover Processors Data Sheet for Consumer Products, Rev. 0.1, 03/2019
6 NXP Semiconductors
Architectural overview
2 Architectural overview
The following subsections provide an architectural overview of the i.MX RT1015 processor system.
2.1 Block diagram
Figure 2 shows the functional modules in the i.MX RT1015 processor system
1
.
.
Figure 2. i.MX RT1015 system block diagram
1. Some modules shown in this block diagram are not offered on all derivatives. See Table 1 for details.
Internal Memory
128 KB OCRAM
shared with TCM
96 KB ROM
External Memory
Connectivity
4 x 4 Keypad
Security
I2C x2
UART x4
GPIO
SPI x2
ADC
System Control
Secure JTAG
PLL / OSC
RTC and Reset
Enhanced DMA
IOMUX
GP Timer x6
CPU Platform
ARM Cortex-M7
16 KB I-cache
16 KB D-cache
FPU
Dual-Channel Quad-SPI
(FlexSPI)
MPU
NVIC
Up to 128 KB TCM
USB2.0 OTG with PHY
ADC (9-Channel) x1
HAB
Quadrature ENC x1
QuadTimer x1
FlexPWM x1
Watch Dog x4
Power Management
DCDC
LDO
Temp Monitor
I2S / SAI x3
Secure RTC Ciphers and RNG
eFUSE
(GPT x2 + PIT x4)
S/PDIF Tx/Rx