Datasheet

Electrical characteristics
i.MX RT1015 Crossover Processors Data Sheet for Consumer Products, Rev. 0.1, 03/2019
NXP Semiconductors 51
Figure 30. Minimum Sample Time Vs Ras (Cas = 10 pF)
4.8 Communication interfaces
The following sections provide the information about communication interfaces.
4.8.1 LPSPI timing parameters
The Low Power Serial Peripheral Interface (LPSPI) provides a synchronous serial bus with master and
slave operations. Many of the transfer attributes are programmable. The following tables provide timing
characteristics for classic LPSPI timing modes.
All timing is shown with respect to 20% V
DD
and 80% V
DD
thresholds, unless noted, as well as input
signal transitions of 3 ns and a 30 pF maximum load on all LPSPI pins.
Table 46. LPSPI master mode timing
Number Symbol Description Min. Max. Units Note
1f
OP
Frequency of operation f
periph
/ 2048 f
periph
/ 2 Hz
1
2t
SPSCK
SPSCK period 2 x t
periph
2048 x t
periph
ns
2
3t
Lead
Enable lead time 1/2 — t
SPSCK
—
4t
Lag
Enable lag time 1/2 — t
SPSCK
—
5t
WSPSCK
Clock (SPSCK) high or low time t
periph
- 30 1024 x t
periph
ns —
6t
SU
Data setup time (inputs) 18 — ns —
7t
HI
Data hold time (inputs) 0 — ns —
8t
V
Data valid (after SPSCK edge( — 15 ns —
9t
HO
Data hold time (outputs) 0 — ns —
10 t
RI
t
FI
Rise time input
Fall time input
—t
periph - 25
ns —
11 t
RO
t
FO
Rise time output
Fall time output
—25ns—