Datasheet

i.MX RT1015 Crossover Processors Data Sheet for Consumer Products, Rev. 0.1, 03/2019
44 NXP Semiconductors
Electrical characteristics
4.6.2 SPDIF timing parameters
The Sony/Philips Digital Interconnect Format (SPDIF) data is sent using the bi-phase marking code. When
encoding, the SPDIF data signal is modulated by a clock that is twice the bit rate of the data signal.
Table 42 and Figure 25 and Figure 26 show SPDIF timing parameters for the Sony/Philips Digital
Interconnect Format (SPDIF), including the timing of the modulating Rx clock (SPDIF_SR_CLK) for
SPDIF in Rx mode and the timing of the modulating Tx clock (SPDIF_ST_CLK) for SPDIF in Tx mode.
Figure 25. SPDIF_SR_CLK timing diagram
Table 42. SPDIF timing parameters
Characteristics Symbol
Timing parameter range
Unit
Min Max
SPDIF_IN Skew: asynchronous inputs, no specs apply — — 0.7 ns
SPDIF_OUT output (Load = 50pf)
• Skew
• Transition rising
• Transition falling
—
—
—
—
—
—
1.5
24.2
31.3
ns
SPDIF_OUT1 output (Load = 30pf)
• Skew
• Transition rising
• Transition falling
—
—
—
—
—
—
1.5
13.6
18.0
ns
Modulating Rx clock (SPDIF_SR_CLK) period srckp 40.0 — ns
SPDIF_SR_CLK high period srckph 16.0 — ns
SPDIF_SR_CLK low period srckpl 16.0 — ns
Modulating Tx clock (SPDIF_ST_CLK) period stclkp 40.0 — ns
SPDIF_ST_CLK high period stclkph 16.0 — ns
SPDIF_ST_CLK low period stclkpl 16.0 — ns
SPDIF_SR_CLK
(Output)
V
M
V
M
srckp
srckph
srckpl