Datasheet

Electrical characteristics
i.MX RT1015 Crossover Processors Data Sheet for Consumer Products, Rev. 0.1, 03/2019
NXP Semiconductors 43
Figure 23. SAI timing—master modes
Figure 24. SAI timing—slave modes
Table 41. Slave mode SAI timing
Num Characteristic Min Max Unit
S11 SAI_BCLK cycle time (input) 4 x t
sys
—ns
S12 SAI_BCLK pulse width high/low (input) 40% 60% BCLK period
S13 SAI_FS input setup before SAI_BCLK 10 — ns
S14 SAI_FA input hold after SAI_BCLK 2 — ns
S15 SAI_BCLK to SAI_TXD/SAI_FS output valid — 20 ns
S16 SAI_BCLK to SAI_TXD/SAI_FS output invalid 0 — ns
S17 SAI_RXD setup before SAI_BCLK 10 — ns
S18 SAI_RXD hold after SAI_BCLK 2 — ns