Datasheet

i.MX RT1015 Crossover Processors Data Sheet for Consumer Products, Rev. 0.1, 03/2019
42 NXP Semiconductors
Electrical characteristics
Figure 22. FlexSPI output timing in DDR mode
4.6 Audio
This section provide information about SAI/I2S and SPDIF.
4.6.1 SAI/I2S switching specifications
This section provides the AC timings for the SAI in master (clocks driven) and slave (clocks input) modes.
All timings are given for non-inverted serial clock polarity (SAI_TCR[TSCKP] = 0, SAI_RCR[RSCKP]
= 0) and non-inverted frame sync (SAI_TCR[TFSI] = 0, SAI_RCR[RFSI] = 0). If the polarity of the clock
and/or the frame sync have been inverted, all the timings remain valid by inverting the clock signal
(SAI_BCLK) and/or the frame sync (SAI_FS) shown in the figures below.
Table 40. Master mode SAI timing
Num Characteristic Min Max Unit
S1 SAI_MCLK cycle time 2 x t
sys
—ns
S2 SAI_MCLK pulse width high/low 40% 60% MCLK period
S3 SAI_BCLK cycle time 4 x t
sys
—ns
S4 SAI_BCLK pulse width high/low 40% 60% BCLK period
S5 SAI_BCLK to SAI_FS output valid — 15 ns
S6 SAI_BCLK to SAI_FS output invalid 0 — ns
S7 SAI_BCLK to SAI_TXD valid — 15 ns
S8 SAI_BCLK to SAI_TXD invalid 0 — ns
S9 SAI_RXD/SAI_FS input setup before SAI_BCLK 15 — ns
S10 SAI_RXD/SAI_FS input hold after SAI_BCLK 0 — ns
T CSS T CK
T DVO
T DHO
T DVO
T DHO
T CSH
SCK
CS
SIO[0:7]