Datasheet

Electrical characteristics
i.MX RT1015 Crossover Processors Data Sheet for Consumer Products, Rev. 0.1, 03/2019
NXP Semiconductors 41
NOTE
T
CSS
and T
CSH
are configured by the FlexSPIn_FLSHAxCR1
register, the default values are shown above. Please refer to the i.MX
RT1015 Reference Manual (IMXRT1015RM) for more details.
Figure 21. FlexSPI output timing in SDR mode
4.5.1.1.2 DDR mode
NOTE
T
CSS
and T
CSH
are configured by the FlexSPIn_FLSHAxCR1
register, the default values are shown above. Please refer to the i.MX
RT1015 Reference Manual (IMXRT1015RM) for more details.
T
CSS
Chip select output setup time 3 x T
CK
-1 — ns
T
CSH
Chip select output hold time 3 x T
CK
+ 2 — ns
1
The actual maximum frequency supported is limited by the FlexSPIn_MCR0[RXCLKSRC] configuration used. Please refer to the FlexSPI SDR input timing
specifications.
Table 39. FlexSPI output timing in DDR mode
Symbol Parameter Min Max Unit
— Frequency of operation
1
1
The actual maximum frequency supported is limited by the FlexSPIn_MCR0[RXCLKSRC] configuration used. Please refer to the FlexSPI SDR input timing
specifications.
—166MHz
T
ck
SCK clock period (FlexSPIn_MCR0[RXCLKSRC] = 0x0) 6.0 — ns
T
DVO
Output data valid time — 2.2 ns
T
DHO
Output data hold time 0.8 — ns
T
CSS
Chip select output setup time 3 x T
CK
/ 2 - 0.7 — ns
T
CSH
Chip select output hold time 3 x T
CK
/ 2 + 0.8 — ns
Table 38. FlexSPI output timing in SDR mode (continued)
Symbol Parameter Min Max Unit
T
CSS
T
CK
TCSH
T DVO
T DHO
T DVO
T DHO
SCK
CS
SIO[0:7]