Datasheet

i.MX RT1015 Crossover Processors Data Sheet for Consumer Products, Rev. 0.1, 03/2019
40 NXP Semiconductors
Electrical characteristics
Figure 19. FlexSPI input timing in DDR mode where FlexSPIn_MCR0[RXCLKSRC] = 0x3 (Case B1)
Figure 20. FlexSPI input timing in DDR mode where FlexSPIn_MCR0[RXCLKSRC] = 0x3 (Case B2)
4.5.1.1 FlexSPI output/write timing
The following sections describe output signal timing for the FlexSPI controller including control signals
and data outputs.
4.5.1.1.1 SDR mode
Table 37. FlexSPI input timing in DDR mode where FlexSPIn_MCR0[RXCLKSRC] = 0x3 (Case B2)
Symbol Parameter Min Max Unit
— Frequency of operation — 166 MHz
T
SCKD
Time from SCK to data valid — — ns
T
SCKD -
T
SCKDQS
Time delta between T
SCKD
and T
SCKDQS
-1 1 ns
Table 38. FlexSPI output timing in SDR mode
Symbol Parameter Min Max Unit
— Frequency of operation — 166
1
MHz
T
ck
SCK clock period 6.0 — ns
T
DVO
Output data valid time — 1 ns
T
DHO
Output data hold time -1 — ns
TSCKD
TSCKDQS
SIO[0:7]
DQS
SCK
T
SCKD
T SCK2DQS
SCK2
SIO[0:7]
DQS
SCK