Datasheet

Electrical characteristics
i.MX RT1015 Crossover Processors Data Sheet for Consumer Products, Rev. 0.1, 03/2019
NXP Semiconductors 39
Figure 18. FlexSPI input timing in DDR mode where FlexSPIn_MCR0[RXCLKSRC] = 0x0, 0x1
4.5.1.0.4 DDR mode with FlexSPIn_MCR0[RXCLKSRC] = 0x3
There are two cases when the memory provides both read data and the read strobe in DDR mode:
• B1–Memory generates both read data and read strobe on SCK edge
• B2–Memory generates read data on SCK edge and generates read strobe on SCK2
edge
Table 35. FlexSPI input timing in DDR mode where FlexSPIn_MCR0[RXCLKSRC] = 0x1
Symbol Parameter Min Max Unit
— Frequency of operation — 66 MHz
T
IS
Setup time for incoming data 2 — ns
T
IH
Hold time for incoming data 1 — ns
Table 36. FlexSPI input timing in DDR mode where FlexSPIn_MCR0[RXCLKSRC] = 0x3 (Case B1)
Symbol Parameter Min Max Unit
— Frequency of operation — 166 MHz
T
SCKD
Time from SCK to data valid — — ns
T
SCKDQS
Time from SCK to DQS — — ns
T
SCKD -
T
SCKDQS
Time delta between T
SCKD
and T
SCKDQS
-1 1 ns
T
IS
T
IH
T
IS
T
IH
SCLK
SIO[0:7]
Internal Sample Clock