Datasheet

i.MX RT1015 Crossover Processors Data Sheet for Consumer Products, Rev. 0.1, 03/2019
38 NXP Semiconductors
Electrical characteristics
NOTE
Timing shown is based on the memory generating read data and read strobe
on the SCK rising edge. The FlexSPI controller samples read data on the
DQS falling edge.
Figure 17. FlexSPI input timing in SDR mode where FlexSPIn_MCR0[RXCLKSRC] = 0X3 (Case A2)
NOTE
Timing shown is based on the memory generating read data on the SCK
falling edge and read strobe on the SCK rising edge. The FlexSPI controller
samples read data on a half cycle delayed DQS falling edge.
4.5.1.0.3 DDR mode with FlexSPIn_MCR0[RXCLKSRC] = 0x0, 0x1
Table 33. FlexSPI input timing in SDR mode where FlexSPIn_MCR0[RXCLKSRC] = 0x3 (Case A2)
Symbol Parameter
Value
Unit
Min Max
— Frequency of operation — 166 MHz
T
SCKD
Time from SCK to data valid — — ns
T
SCKDQS
Time from SCK to DQS — — ns
T
SCKD -
T
SCKDQS
Time delta between T
SCKD
and T
SCKDQS
-2 2 ns
Table 34. FlexSPI input timing in DDR mode where FlexSPIn_MCR0[RXCLKSRC] = 0x0
Symbol Parameter Min Max Unit
— Frequency of operation — 30 MHz
T
IS
Setup time for incoming data 8.67 — ns
T
IH
Hold time for incoming data 0 — ns
T
SCKDQS
TSCKD
SCK
SIO[0:7]
DQS
Internal Sample Clock
T
SCKDQS
TSCKD
T
SCKDQS
TSCKD