Datasheet

Electrical characteristics
i.MX RT1015 Crossover Processors Data Sheet for Consumer Products, Rev. 0.1, 03/2019
NXP Semiconductors 37
Figure 15. FlexSPI input timing in SDR mode where FlexSPIn_MCR0[RXCLKSRC] = 0X0, 0X1
NOTE
Timing shown is based on the memory generating read data on the SCK
falling edge, and FlexSPI controller sampling read data on the falling edge.
4.5.1.0.2 SDR mode with FlexSPIn_MCR0[RXCLKSRC] = 0x3
There are two cases when the memory provides both read data and the read strobe in SDR mode:
• A1–Memory generates both read data and read strobe on SCK rising edge (or falling
edge)
• A2–Memory generates read data on SCK falling edge and generates read strobe on
SCK rising edgeSCK rising edge
Figure 16. FlexSPI input timing in SDR mode where FlexSPIn_MCR0[RXCLKSRC] = 0X3 (Case A1)
Table 32. FlexSPI input timing in SDR mode where FlexSPIn_MCR0[RXCLKSRC] = 0x3 (Case A1)
Symbol Parameter
Value
Unit
Min Max
— Frequency of operation — 166 MHz
T
SCKD
Time from SCK to data valid — — ns
T
SCKDQS
Time from SCK to DQS — — ns
T
SCKD -
T
SCKDQS
Time delta between T
SCKD
and T
SCKDQS
-2 2 ns
T IS T IH
SCK
SIO[0:7]
T IS T IH
Internal Sample Clock
T SCKDQS
SCK
SIO[0:7]
DQS
T SCKD
T SCKDQS
T SCKD