NXP Semiconductors Data Sheet: Technical Data Document Number: IMXRT1015CEC Rev. 0.1, 03/2019 MIMXRT1015DAF5A i.MX RT1015 Crossover Processors Data Sheet for Consumer Products Package Information Plastic Package 100-Pin LQFP, 14 x 14 mm, 0.5 mm pitch Ordering Information See Table 1 on page 4 1 i.MX RT1015 introduction The i.MX RT1015 is a processor of i.
i.MX RT1015 introduction The i.MX RT1015 is specifically useful for applications such as: • Industrial • Motor Control • Home Appliance • Audio • IoT 1.1 Features The i.
i.MX RT1015 introduction – Each support standard capture and compare operation – Quadrature decoder integrated — One FlexPWM – Up to 8 individual PWM channels – 16-bit resolution PWM suitable for Motor Control applications — One Quadrature Encoder/Decoder Each i.
i.MX RT1015 introduction • • • • Bus Encryption Engine (BEE) — AES-128, ECB, and CTR mode — On-the-fly QSPI Flash decryption True random number generation (TRNG) Secure Non-Volatile Storage (SNVS) — Secure real-time clock (RTC) — Zero Master Key (ZMK) Secure JTAG Controller (SJC) NOTE The actual feature set depends on the part numbers as described in Table 1. Functions such as display and camera interfaces, connectivity interfaces, and security features are not offered on all derivatives. 1.
i.MX RT1015 introduction Ensure to have the proper data sheet for specific part by verifying the temperature grade (junction) field and matching it to the proper data sheet. If there are any questions, visit the web page nxp.com/IMXRT or contact an NXP representative for details. M IMX XX @ ## % + VV $ A M Silicon Rev A Prototype Samples P A0 A Mass Production M Special S Qualification Level Part # series XX i.
Architectural overview 2 Architectural overview The following subsections provide an architectural overview of the i.MX RT1015 processor system. 2.1 Block diagram Figure 2 shows the functional modules in the i.MX RT1015 processor system1.
Modules list 3 Modules list The i.MX RT1015 processors contain a variety of digital and analog modules. Table 2 describes these modules in alphabetical order. Table 2. i.MX RT1015 modules list Block mnemonic Block name Subsystem Brief description ADC1 Analog to Digital Converter Analog The ADC is a 12-bit general purpose analog to digital converter.
Modules list Table 2. i.MX RT1015 modules list (continued) Block mnemonic Block name Subsystem Brief description ENC Quadrature Encoder/Decoder Timer Peripherals The enhanced quadrature encoder/decoder module provides interfacing capability to position/speed sensors. There are five input signals: PHASEA, PHASEB, INDEX, TRIGGER, and HOME. This module is used to decode shaft position, revolution count, and speed.
Modules list Table 2. i.MX RT1015 modules list (continued) Block mnemonic Block name Subsystem Brief description GPT1 GPT2 General Purpose Timer Timer Peripherals Each GPT is a 32-bit “free-running” or “set and forget” mode timer with programmable prescaler and compare and capture register. A timer counter value can be captured using an external event and can be configured to trigger a capture event on either the leading or trailing edges of an input pulse.
Modules list Table 2. i.MX RT1015 modules list (continued) Block mnemonic Block name Subsystem Brief description QuadTimer1 QuadTimer Timer Peripherals The quad-timer provides four timer channels with a variety of controls affecting both individual and multi-channel features.
Modules list Table 2. i.MX RT1015 modules list (continued) Block mnemonic Block name Subsystem Brief description SPDIF Sony Philips Digital Interconnect Format Multimedia Peripherals A standard audio file transfer format, developed jointly by the Sony and Phillips corporations. Has Transmitter and Receiver functionality. Temp Monitor Temperature Monitor Analog The temperature sensor implements a temperature sensor/conversion function based on a temperature-dependent voltage to time conversion.
Modules list 3.1 Special signal considerations Table 3 lists special signal considerations for the i.MX RT1015 processors. The signal names are listed in alphabetical order. The package contact assignments can be found in Section 6, Package information and contact assignments. Signal descriptions are provided in the i.MX RT1015 Reference Manual (IMXRT1015RM). Table 3. Special signal considerations Signal name Remarks DCDC_PSWITCH PAD is in DCDC_IN domain and connected the ground to bypass DCDC.
Modules list Table 3. Special signal considerations (continued) Signal name Remarks POR_B This cold reset negative logic input resets all modules and logic in the IC. May be used in addition to internally generated power on reset signal (logical AND, both internal and external signals are considered active low). ONOFF ONOFF can be configured in debounce, off to on time, and max time-out configurations. The debounce and off to on time configurations supports 0, 50, 100 and 500 ms.
Electrical characteristics 4 Electrical characteristics This section provides the device and module-level electrical characteristics for the i.MX RT1015 processors. 4.1 Chip-level conditions This section provides the device-level electrical characteristics for the IC. See Table 6 for a quick reference to the individual tables and sections. Table 6. i.
Electrical characteristics Table 7. Absolute maximum ratings (continued) ESD Damage Immunity: Vesd Human Body Model (HBM) Charge Device Model (CDM) — — 1000 500 V Input/Output Voltage range Vin/Vout -0.5 OVDD + 0.31 V Storage Temperature range TSTORAGE -40 150 1 o C OVDD is the I/O supply voltage. 4.1.2 Thermal resistance Following sections provide the thermal resistance data. 4.1.2.
Electrical characteristics 4.1.3 Operating ranges Table 9 provides the operating ranges of the i.MX RT1015 processors. For details on the chip's power structure, see the “Power Management Unit (PMU)” chapter of the i.MX RT1015 Reference Manual (IMXRT1015RM). Table 9. Operating ranges Parameter Description Run Mode Operating Conditions Symbol Min Typ Max1 Unit Comment VDD_SOC_IN Overdrive 1.25 — 1.3 V — VDD_SOC_IN M7 core at 396 MHz 1.15 — 1.3 V — M7 core at 132 MHz 1.15 — 1.
Electrical characteristics Table 9. Operating ranges (continued) Temperature Operating Ranges Junction temperature Tj Standard Commercial 0 — 95 o C See the application note, i.MX RT1015 Product Lifetime Usage Estimates for information on product lifetime (power-on years) for this processor. 1 Applying the maximum voltage results in maximum power consumption and heat generation. NXP recommends a voltage set point = (Vmin + the supply tolerance). This result in an optimized power/speed ratio.
Electrical characteristics • — Starts up quicker than 32 kHz crystal oscillator External crystal oscillator with on-chip support circuit: — At power up, ring oscillator is utilized. After crystal oscillator is stable, the clock circuit switches over to the crystal oscillator automatically.
Electrical characteristics 4.1.6 Low power mode supply currents Table 13 shows the current core consumption (not including I/O) of i.MX RT1015 processors in selected low power modes. Table 13. Low power mode current and power consumption Mode Test Conditions SYSTEM IDLE LOW POWER IDLE SUSPEND (DSM) SNVS (RTC) 1 Typical1 Supply Units • LDO_ARM and LDO_SOC set to the Bypass mode • LDO_2P5 set to 2.5 V, LDO_1P1 set to 1.
Electrical characteristics NOTE The currents on the VDD_HIGH_CAP and VDD_USB_CAP were identified to be the voltage divider circuits in the USB-specific level shifters. 4.2 System power and clocks This section provide the information about the system power and clocks. 4.2.1 Power supplies requirements and restrictions The system design must comply with power-up sequence, power-down sequence, and steady state guidelines as described in this section to guarantee the reliable operation of the device.
Electrical characteristics 4.2.1.2 Power-down sequence The following restrictions must be followed: • VDD_SNVS_IN supply must be turned off after any other power supply or be connected (shorted) with VDD_HIGH_IN supply. • If a coin cell is used to power VDD_SNVS_IN, then ensure that it is removed after any other supply is switched off. 4.2.1.3 Power supplies usage All I/O pins should not be externally driven while the I/O power supply for the pin (NVCC_xxx) is OFF.
Electrical characteristics 4.2.2.2 4.2.2.2.1 Regulators for analog modules LDO_1P1 The LDO_1P1 regulator implements a programmable linear-regulator function from VDD_HIGH_IN (see Table 9 for minimum and maximum input requirements). Typical Programming Operating Range is 1.0 V to 1.2 V with the nominal default setting as 1.1 V. The LDO_1P1 supplies the USB Phy, and PLLs.
Electrical characteristics For additional information, see the i.MX RT1015 Reference Manual (IMXRT1015RM). 4.2.2.2.4 DCDC DCDC can be configured to operate on power-save mode when the load current is less than 50 mA. During the power-save mode, the converter operates with reduced switching frequency in PFM mode and with a minimum quiescent current to maintain high efficiency. DCDC can detect the peak current in the P-channel switch.
Electrical characteristics 4.2.3.3 Ethernet PLL Table 17. Ethernet PLL’s electrical parameters Parameter Value Clock output range 1 GHz Reference clock 25 MHz Lock time < 11250 reference cycles 4.2.3.4 USB PLL Table 18. USB PLL’s electrical parameters Parameter Value Clock output range 480 MHz PLL output Reference clock 24 MHz Lock time < 383 reference cycles 4.2.4 4.2.4.
Electrical characteristics • • Average Discharge Voltage is 2.5 V Maximum Charge Current is 0.6 mA For a charge voltage of 3.2 V, Rs = (3.2-2.5)/0.6 m = 1.17 k. Table 19. OSC32K main characteristics Min Fosc — Typ Max Comments 32.768 KHz — This frequency is nominal and determined mainly by the crystal selected. 32.0 K would work as well. Current consumption — 4 A — The 4 A is the consumption of the oscillator alone (OSC32k).
Electrical characteristics Figure 3. Circuit for parameters Voh and Vol for I/O cells 4.3.1.1 XTALI and RTC_XTALI (clock inputs) DC parameters Table 20 shows the DC parameters for the clock inputs. Table 20. XTALI and RTC_XTALI DC parameters1 Parameter Symbol Test Conditions XTALI high-level DC input voltage Vih — 0.8 x NVCC_PLL NVCC_PLL V XTALI low-level DC input voltage Vil — 0 0.2 V RTC_XTALI high-level DC input voltage Vih — 0.8 1.
Electrical characteristics Table 21. Single voltage GPIO DC parameters (continued) Parameter Symbol Test Conditions Min Max Units Input Hysteresis (NVCC_XXXX= 1.8V) VHYS_LowV NVCC_XXXX = 1.8 V DD 250 — mV Input Hysteresis (NVCC_XXXX=3.3V) VHYS_High VDD NVCC_XXXX = 3.3 V 250 — mV Schmitt trigger VT+2,3 VTH+ — 0.5 x NVCC_XXXX — mV Schmitt trigger VT-2,3 VTH- — — 0.
Electrical characteristics 80% 80% 20% 0V 20% Output (at pad) tf tr OVDD Figure 5. Output transition time waveform 4.3.2.1 General purpose I/O AC parameters The I/O AC parameters for GPIO in slow and fast modes are presented in the Table 22 and Table 23, respectively. Note that the fast or slow I/O behavior is determined by the appropriate control bits in the IOMUXC control registers. Table 22. General purpose I/O AC parameters 1.
Electrical characteristics 4.3.3 Output buffer impedance parameters This section defines the I/O impedance parameters of the i.MX RT1015 processors for the following I/O types: • Single Voltage General Purpose I/O (GPIO) NOTE GPIO I/O output driver impedance is measured with “long” transmission line of impedance Ztl attached to I/O pad and incident wave launched into transmission line. Rpu/Rpd and Ztl form a voltage divider that defines specific voltage of incident wave relative to NVCC_XXXX.
Electrical characteristics OVDD PMOS (Rpu) Ztl , L = 20 inches ipp_do pad predriver Cload = 1p NMOS (Rpd) OVSS U,(V) Vin (do) VDD t,(ns) 0 U,(V) Vout (pad) OVDD Vref2 Vref1 Vref t,(ns) 0 Rpu = Vovdd - Vref1 Vref1 Ztl Rpd = Vref2 Vovdd - Vref2 Ztl Figure 6. Impedance matching load for measurement i.MX RT1015 Crossover Processors Data Sheet for Consumer Products, Rev. 0.
Electrical characteristics 4.3.3.1 Single voltage GPIO output buffer impedance Table 24 shows the GPIO output buffer impedance (NVCC_XXXX 1.8 V). Table 24. GPIO output buffer average impedance (NVCC_XXXX 1.8 V) Parameter Output Driver Impedance Symbol Drive strength (DSE) Typ value 001 010 011 100 101 110 111 Rdrv Unit 260 130 88 65 52 43 37 Table 25 shows the GPIO output buffer impedance (NVCC_XXXX 3.3 V). Table 25. GPIO Output buffer average impedance (NVCC_XXXX 3.
Electrical characteristics 4.4.2 WDOG reset timing parameters Figure 8 shows the WDOG reset timing and Table 27 lists the timing parameters. WDOGn_B (Output) CC3 Figure 8. WDOGn_B timing diagram Table 27. WDOGn_B timing parameters ID CC3 Parameter Min Duration of WDOGn_B Assertion Max 1 — Unit RTC_XTALI cycle NOTE RTC_XTALI is approximately 32 kHz. RTC_XTALI cycle is one period or approximately 30 s.
Electrical characteristics JTAG_TCK (Input) VIH VIL SJ4 Data Inputs SJ5 Input Data Valid SJ6 Data Outputs Output Data Valid SJ7 Data Outputs SJ6 Data Outputs Output Data Valid Figure 10. Boundary scan (JTAG) timing diagram i.MX RT1015 Crossover Processors Data Sheet for Consumer Products, Rev. 0.
Electrical characteristics JTAG_TCK (Input) VIH VIL SJ8 JTAG_TDI JTAG_TMS (Input) SJ9 Input Data Valid SJ10 JTAG_TDO (Output) Output Data Valid SJ11 JTAG_TDO (Output) SJ10 JTAG_TDO (Output) Output Data Valid Figure 11. Test access port timing diagram JTAG_TCK (Input) JTAG_TRST_B (Input) SJ13 SJ12 Figure 12. JTAG_TRST_B timing diagram Table 28. JTAG timing ID All frequencies Parameter1,2 Unit Min Max SJ0 JTAG_TCK frequency of operation 1/(3•TDC)1 0.
Electrical characteristics Table 28. JTAG timing (continued) All frequencies Parameter1,2 ID Unit Min Max SJ9 JTAG_TMS, JTAG_TDI data hold time 25 — ns SJ10 JTAG_TCK low to JTAG_TDO data valid — 44 ns SJ11 JTAG_TCK low to JTAG_TDO high impedance — 44 ns SJ12 JTAG_TRST_B assert time 100 — ns SJ13 JTAG_TRST_B set-up time to JTAG_TCK low 40 — ns 1 2 TDC = target frequency of SJC VM = mid-point voltage 4.4.4 Debug trace timing specifications Table 29.
Electrical characteristics ARM_TRACE_CLK T7 T7 T8 T8 ARM_TRACE0-3 Figure 14. Trace data specifications 4.5 External memory interface The following sections provide information about external memory interfaces.FlexSPI parameters Measurements are with a load 15 pf and input slew rate of 1 V/ns. 4.5.
Electrical characteristics SCK TIS TIH TIS TIH SIO[0:7] Internal Sample Clock Figure 15. FlexSPI input timing in SDR mode where FlexSPIn_MCR0[RXCLKSRC] = 0X0, 0X1 NOTE Timing shown is based on the memory generating read data on the SCK falling edge, and FlexSPI controller sampling read data on the falling edge. 4.5.1.0.
Electrical characteristics NOTE Timing shown is based on the memory generating read data and read strobe on the SCK rising edge. The FlexSPI controller samples read data on the DQS falling edge. Table 33.
Electrical characteristics Table 35. FlexSPI input timing in DDR mode where FlexSPIn_MCR0[RXCLKSRC] = 0x1 Symbol Parameter Min Max Unit — Frequency of operation — 66 MHz TIS Setup time for incoming data 2 — ns TIH Hold time for incoming data 1 — ns SCLK TIS TIH TIS TIH SIO[0:7] Internal Sample Clock Figure 18. FlexSPI input timing in DDR mode where FlexSPIn_MCR0[RXCLKSRC] = 0x0, 0x1 4.5.1.0.
Electrical characteristics SCK TSCKD SIO[0:7] TSCKDQS DQS Figure 19. FlexSPI input timing in DDR mode where FlexSPIn_MCR0[RXCLKSRC] = 0x3 (Case B1) Table 37. FlexSPI input timing in DDR mode where FlexSPIn_MCR0[RXCLKSRC] = 0x3 (Case B2) Symbol Parameter Min Max Unit — Frequency of operation — 166 MHz TSCKD Time from SCK to data valid — — ns TSCKD - TSCKDQS Time delta between TSCKD and TSCKDQS -1 1 ns SCK TSCKD SIO[0:7] SCK2 TSCK2DQS DQS Figure 20.
Electrical characteristics Table 38. FlexSPI output timing in SDR mode (continued) Symbol Parameter Min Max Unit TCSS Chip select output setup time 3 x TCK -1 — ns TCSH Chip select output hold time 3 x TCK + 2 — ns 1 The actual maximum frequency supported is limited by the FlexSPIn_MCR0[RXCLKSRC] configuration used. Please refer to the FlexSPI SDR input timing specifications. NOTE TCSS and TCSH are configured by the FlexSPIn_FLSHAxCR1 register, the default values are shown above.
Electrical characteristics SCK T CSS T CK TCSH CS TDVO SIO[0:7] TDHO TDVO TDHO Figure 22. FlexSPI output timing in DDR mode 4.6 Audio This section provide information about SAI/I2S and SPDIF. 4.6.1 SAI/I2S switching specifications This section provides the AC timings for the SAI in master (clocks driven) and slave (clocks input) modes.
Electrical characteristics Figure 23. SAI timing—master modes Table 41.
Electrical characteristics 4.6.2 SPDIF timing parameters The Sony/Philips Digital Interconnect Format (SPDIF) data is sent using the bi-phase marking code. When encoding, the SPDIF data signal is modulated by a clock that is twice the bit rate of the data signal.
Electrical characteristics stclkp stclkpl SPDIF_ST_CLK VM stclkph VM (Input) Figure 26. SPDIF_ST_CLK timing diagram 4.7 Analog The following sections provide information about analog interfaces. 4.7.1 DCDC Table 43 introduces the DCDC electrical specification. Table 43. DCDC electrical specifications Mode Buck mode only, one output Notes Input voltage 3.3 V ± 10% Output voltage 1.1 V Configurable 0.8 ~ 1.
Electrical characteristics 4.7.2.1 12-bit ADC electrical characteristics The section provide information about 12-bit ADC electrical characteristics. 4.7.2.1.1 12-bit ADC operating conditions Table 44. 12-bit ADC operating conditions Characteristic Supply voltage Conditions Symb Typ1 Min Max Unit Comment Absolute VDDA 3.0 - 3.6 V — Delta to VDD (VDD-VDDA)2 VDDA -100 0 100 mV — Ground voltage Delta to VSS (VSS-VSSAD) VSSAD -100 0 100 mV — Ref Voltage High — VDDA 1.
Electrical characteristics Figure 27. 12-bit ADC input impedance equivalency diagram 12-bit ADC characteristics Table 45. 12-bit ADC characteristics (VREFH = VDDA, VREFL = VSSAD) Characteristic Supply Current Conditions1 ADLPC=1, ADHSC=0 Symb IDDA Typ2 Min — 250 ADLPC=0, ADHSC=0 350 ADLPC=0, ADHSC=1 400 Max Unit Comment — µA ADLSMP = 0, ADSTS = 10, ADCO = 1 Supply Current Stop, Reset, Module Off IDDA — 0.01 0.
Electrical characteristics Table 45.
Electrical characteristics Table 45. 12-bit ADC characteristics (VREFH = VDDA, VREFL = VSSAD) (continued) Characteristic Conversion Time Total Unadjusted Error Differential Non-Linearity Conditions1 ADLSMP=0 ADSTS=00 — Typ2 0.7 0.75 ADLSMP=0 ADSTS=10 0.8 ADLSMP=0 ADSTS=11 0.85 ADLSMP=1 ADSTS=00 0.95 ADLSMP=1 ADSTS=01 1.05 ADLSMP=1 ADSTS=10 1.15 ADLSMP=1, ADSTS=11 1.
Electrical characteristics 2 Typical values assume VDDAD = 3.0 V, Temp = 25°C, Fadck=20 MHz unless otherwise stated. Typical values are for reference only and are not tested in production. NOTE The ADC electrical spec is met with the calibration enabled configuration. Figure 28. Minimum Sample Time Vs Ras (Cas = 2 pF) Figure 29. Minimum Sample Time Vs Ras (Cas = 5 pF) i.MX RT1015 Crossover Processors Data Sheet for Consumer Products, Rev. 0.
Electrical characteristics Figure 30. Minimum Sample Time Vs Ras (Cas = 10 pF) 4.8 Communication interfaces The following sections provide the information about communication interfaces. 4.8.1 LPSPI timing parameters The Low Power Serial Peripheral Interface (LPSPI) provides a synchronous serial bus with master and slave operations. Many of the transfer attributes are programmable. The following tables provide timing characteristics for classic LPSPI timing modes.
Electrical characteristics 1 Absolute maximum frequency of operation (fop) is 30 MHz. The clock driver in the LPSPI module for fperiph must be guaranteed this limit is not exceeded. 2 tperiph = 1 / fperiph 1 SS (OUTPUT) 3 2 SPSCK (CPOL=0) (OUTPUT) 12 13 12 13 4 5 5 SPSCK (CPOL=1) (OUTPUT) 6 7 2 MSB IN SIN (INPUT) BIT 6 . . . 1 LSB IN 10 SOUT (OUTPUT) 2 MSB OUT 11 BIT 6 . . . 1 LSB OUT 1. If configured as an output. 2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.
Electrical characteristics Table 47. LPSPI slave mode timing Number Symbol Description Min. Max. Units Note 1 fOP Frequency of operation 0 fperiph / 2 Hz 1 2 tSPSCK SPSCK period 4 x tperiph — ns 2 3 tLead Enable lead time 1 — tperiph — 4 tLag Enable lag time 1 — tperiph — 5 tWSPSCK Clock (SPSCK) high or low time tperiph - 30 — ns — 6 tSU Data setup time (inputs) 2.5 — ns — 7 tHI Data hold time (inputs) 3.
Electrical characteristics 66 ,1387 636&. &32/ ,1387 636&. &32/ ,1387 0,62 287387 VHH QRWH 6/$9( 06% 287 026, ,1387 %,7 6/$9( /6% 287 %,7 /6% ,1 06% ,1 Figure 34. LPSPI slave mode timing (CPHA = 1) 4.8.2 LPI2C module timing parameters This section describes the timing parameters of the LPI2C module. Table 48.
Electrical characteristics 4.8.4 USB PHY parameters This section describes the USB-OTG PHY parameters. The USB PHY meets the electrical compliance requirements defined in the Universal Serial Bus Revision 2.0 OTG with the following amendments. • USB ENGINEERING CHANGE NOTICE — Title: 5V Short Circuit Withstand Requirement Change — Applies to: Universal Serial Bus Specification, Revision 2.0 • Errata for USB Revision 2.
Electrical characteristics Table 50. Quad Timer Timing Characteristic Min1 Symbo Max Unit Timer input period TIN 2T + 6 — ns Timer input high/low period TINHL 1T + 3 — ns Timer output period TOUT 33 — ns Timer output high/low period TOUTHL 16.7 — ns 1 See Figure T = clock cycle. For 60 MHz operation, T = 16.7 ns. 4IMER )NPUTS 4 ). 4 ).(, 4 ).(, 4 /54 4 /54(, 4 /54(, 4IMER /UTPUTS Figure 35. Quad timer timing i.
Boot mode configuration 5 Boot mode configuration This section provides information on boot mode configuration pins allocation and boot devices interfaces allocation. 5.1 Boot mode configuration pins Table 51 provides boot options, functionality, fuse values, and associated pins. Several input pins are also sampled at reset and can be used to override fuse values, depending on the value of BT_FUSE_SEL fuse.
Boot mode configuration Table 52. Boot through FlexSPI (continued) PAD Name IO Function Mux Mode Comments GPIO_SD_B1_01 flexspi.B_SCLK ALT 1 — GPIO_SD_B0_05 flexspi.B_DQS ALT 6 — GPIO_SD_B0_04 flexspi.B_SS0_B ALT 6 — GPIO_SD_B0_01 flexspi.B_SS1_B ALT 6 — GPIO_SD_B1_05 flexspi.A_DQS ALT 1 — GPIO_SD_B1_11 flexspi.A_SS0_B ALT 1 — GPIO_SD_B0_00 flexspi.A_SS1_B ALT 6 — GPIO_SD_B1_07 flexspi.A_SCLK ALT 1 — GPIO_SD_B1_08 flexspi.A_DATA[0] ALT 1 — GPIO_SD_B1_10 flexspi.
Boot mode configuration Table 56. Boot through SPI-2 PAD Name IO Function Mux Mode Comments GPIO_SD_B1_07 lpspi2.SCK ALT 4 — GPIO_SD_B1_08 lpspi2.SDO ALT 4 — GPIO_SD_B1_09 lpspi2.SDI ALT 4 — GPIO_SD_B1_06 lpspi2.PCS0 ALT 4 — Table 57. Boot through UART1 PAD Name IO Function Mux Mode Comments GPIO_AD_B0_06 lpuart1.TX ALT 2 — GPIO_AD_B0_07 lpuart1.RX ALT 2 — GPIO_AD_B0_08 lpuart1.CTS_B ALT 2 — GPIO_AD_B0_09 lpuart1.RTS_B ALT 2 — Table 58.
Package information and contact assignments 6 Package information and contact assignments This section includes the contact assignment information and mechanical package drawing. 6.1 6.1.1 14 x 14 mm package information 14 x 14 mm, 0.5 mm pitch, ball matrix Figure 36 shows the top and side views of the 14 x 14 mm LQFP package. i.MX RT1015 Crossover Processors Data Sheet for Consumer Products, Rev. 0.
Package information and contact assignments EM 3M M %M M M EM M <'6:M 3M M M M M 7'0M M '0 F KM A' DM L EM IM JM M M J : <'0#M 6+ 0 M H M Figure 36. 14 x 14 mm LQFP, case x package top and side Views i.MX RT1015 Crossover Processors Data Sheet for Consumer Products, Rev. 0.
Package information and contact assignments 6.1.2 14 x 14 mm supplies contact assignments and functional contact assignments Table 59 shows the device connection list for ground, sense, and reference contact signals. Table 59.
Package information and contact assignments Table 60. 14 x 14 mm functional contact assignments (continued) GPIO_AD_B0_05 73 NVCC_GPIO Digital GPIO ALT0 jtag_mux.TRSTB Input 47 K PU GPIO_AD_B0_06 72 NVCC_GPIO Digital GPIO ALT5 GPIO1.IO[6] Input Keeper GPIO_AD_B0_07 68 NVCC_GPIO Digital GPIO ALT5 GPIO1.IO[7] Input Keeper GPIO_AD_B0_08 67 NVCC_GPIO Digital GPIO ALT5 GPIO1.IO[8] Input Keeper GPIO_AD_B0_09 66 NVCC_GPIO Digital GPIO ALT5 GPIO1.
Package information and contact assignments Table 60. 14 x 14 mm functional contact assignments (continued) GPIO_EMC_08 2 NVCC_GPIO Digital GPIO ALT5 GPIO2.IO[8] Input Keeper GPIO_EMC_09 1 NVCC_GPIO Digital GPIO ALT5 GPIO2.IO[9] Input Keeper GPIO_EMC_16 100 NVCC_GPIO Digital GPIO ALT6 src.BOOT_MODE[0] Input 100 k PD GPIO_EMC_17 99 NVCC_GPIO Digital GPIO ALT6 src.BOOT_MODE[1] Input 100 k PD GPIO_EMC_18 98 NVCC_GPIO Digital GPIO ALT5 GPIO2.
Package information and contact assignments Table 60. 14 x 14 mm functional contact assignments (continued) GPIO_SD_B1_03 16 NVCC_GPIO Digital GPIO ALT5 GPIO3.IO[23] Input Keeper GPIO_SD_B1_04 15 NVCC_GPIO Digital GPIO ALT5 GPIO3.IO[24] Input Keeper GPIO_SD_B1_05 14 NVCC_GPIO Digital GPIO ALT5 GPIO3.IO[25] Input Keeper GPIO_SD_B1_06 13 NVCC_GPIO Digital GPIO ALT5 GPIO3.IO[26] Input Keeper GPIO_SD_B1_07 12 NVCC_GPIO Digital GPIO ALT5 GPIO3.
Package information and contact assignments 6.1.3 14 x 14 mm package pin assignments '0)/?%-#? '0)/?%-#? 633 6$$?3/#?). '0)/?%-#? '0)/?%-#? '0)/?%-#? '0)/?%-#? '0)/?%-#? '0)/?%-#? '0)/?%-#? '0)/?%-#? '0)/?%-#? 6$$?3/#?). .6##?'0)/ 633 '0)/?!$?" ? .
Revision history 7 Revision history Table 61 provides a revision history for this data sheet. Table 61. i.MX RT1015 data sheet document revision history Rev. Number Date Rev. 0.1 03/2019 Substantive Change(s) • • • • • • • • • • Rev. 0 01/2019 Added audio information in the Section 1, i.MX RT1015 introduction Updated FlexPWMs and Quadrature Encoder/Decoder in the Section 1.1, Features Updated the Table 1, Ordering information Updated keypad and GP timer numbers in the Figure 2, "i.
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