Datasheet

Electrical characteristics
i.MX 8QuadXPlus and 8DualXPlus Automotive and Infotainment Applications Processors, Rev. 0, 11/2018
PRELIMINARY NXP Semiconductors92
Figure 48. Boundary system (JTAG) timing diagram
Figure 49. Test Access Port Timing Diagram
JTAG_TCK
(Input)
Data
Inputs
Data
Outputs
Data
Outputs
Data
Outputs
VIH
VIL
Input Data Valid
Output Data Valid
Output Data Valid
SJ4
SJ5
SJ6
SJ7
SJ6
JTAG_TCK
(Input)
JTAG_TDI
(Input)
JTAG_TDO
(Output)
JTAG_TDO
(Output)
JTAG_TDO
(Output)
VIH
VIL
Input Data Valid
Output Data Valid
Output Data Valid
JTAG_TMS
SJ8 SJ9
SJ10
SJ11
SJ10