Datasheet
Electrical characteristics
i.MX 8QuadXPlus and 8DualXPlus Automotive and Infotainment Applications Processors, Rev. 0, 11/2018
PRELIMINARY NXP Semiconductors88
Table 83. FlexSPI timings with FlexSPI
n
_MCR0[RXCLKSRC] = 0x1 (SDR mode)
ID Parameter Min Max Unit
— QSPI
x
[A/B]_SCLK Cycle frequency — 166 MHz
t1 QSPI
x
[A/B]_SCLK High or Low Time 2.7 — ns
t2 QSPI
x
[A/B]_SSy_B pulse width 1 — SCLK
t3 QSPI
x
[A/B]_SSy_B Lead Time
1
1
Timing is controlled from FLSH
x
CR1 register (
x
=A1, A2, B1, or B2).
TCSS+0.5 — SCLK
t4 QSPI
x
[A/B]_SSy_B Lag Time
1
TCSH — SCLK
t5 QSPI
x
[A/B]_DATA
y
output Delay — 1 ns
t6 QSPI
x
[A/B]_DATA
y
Setup Time 1 — ns
t7 QSPI
x
[A/B]_DATA
y
Hold Time 2 — ns
Table 84. FlexSPI timings with FlexSPI
n
_MCR0[RXCLKSRC] = 0x3 (SDR mode)
ID Parameter Min Max Unit
— QSPI
x
[A/B]_DQS Cycle frequency — 200 MHz
t1 QSPI
x
[A/B]_SCLK High or Low Time 2.25 — ns
t2 QSPI
x
[A/B]_SS
y
_B pulse width
1
1
Minimum is 2 SCLK cycles even if CSINTERVAL value is less than 2.
CSINTERVAL — SCLK
t3 QSPI
x
[A/B]_SS
y
_B Lead Time
2
2
Timing is controlled from FLSH
x
CR1 register (
x
=A1, A2, B1, or B2).
TCSS+0.5 — SCLK
t4 QSPI
x
[A/B]_SS
y
_B Lag Time
2
TCSH — SCLK
t5 QSPI
x
[A/B]_DATA
y
output Delay — 1 ns
t8 QSPI
x
[A/B]_DQS / QSPI
x
[A/B]_DATA
y
delta -0.65 0.65 ns