Datasheet

Electrical characteristics
i.MX 8QuadXPlus and 8DualXPlus Automotive and Infotainment Applications Processors, Rev. 0, 11/2018
PRELIMINARYNXP Semiconductors 77
4.10.8.2 LVDS display bridge (LDB) module electrical specifications
The MIPI DSI/LVDS interface is compatible with TIA/EIA 644-A standard. For more details, see
TIA/EIA STANDARD 644-A, “Electrical Characteristics of Low Voltage Differential Signaling (LVDS)
Interface Circuits.”
4.10.8.3 MIPI-DSI HS-TX specifications
Table 67. LVDS Display Bridge (LDB) Electrical Specifications
Parameter Symbol Test Condition Min Max Units
Differential Voltage Output Voltage V
OD
100 Ω Differential load 0.25 0.4 V
Output Voltage High Voh 100 Ω differential load
(0 V Diff—Output High Voltage static)
—1.475V
Output Voltage Low Vol 100 Ω differential load
(0 V Diff—Output Low Voltage static)
0.925 V
Offset Static Voltage V
OS
Two 49.9 Ω resistors in series between
N-P terminal, with output in either Zero or
One state, the voltage measured between
the 2 resistors.
1.125 1.275 V
VOS Differential V
OSDIFF
Difference in V
OS
between a One and a
Zero state
——mV
Output short-circuited to GND ISA ISB With the output common shorted to GND 40 mA
Output short current ISAB 12 mA
Table 68. MIPI high-speed transmitter DC specifications
Symbol Parameter Min Typ Max Unit
V
CMTX
1
1
Value when driving into load impedance anywhere in the Z
ID
range.
High Speed Transmit Static Common Mode Voltage 150 200 250 mV
|ΔV
CMTX
|
(1,0)
V
CMTX
mismatch when Output is Differential-1 or Differential-0 5 mV
|V
OD
|
1
High Speed Transmit Differential Voltage 140 200 270 mV
|ΔV
OD
|V
OD
mismatch when Output is Differential-1 or Differential-0 10 mV
V
OHHS
1
High Speed Output High Voltage 360 mV
Z
OS
Single Ended Output Impedance 40 50 62.5 Ω
ΔZ
OS
Single Ended Output Impedance Mismatch 10 %