Datasheet

Electrical characteristics
i.MX 8QuadXPlus and 8DualXPlus Automotive and Infotainment Applications Processors, Rev. 0, 11/2018
PRELIMINARYNXP Semiconductors 69
4.10.4.4 HS200 Mode Timing
The following figure depicts the timing of HS200 mode, and Table 60 lists the HS200 timing
characteristics.
Figure 31. HS200 Mode Timing
Table 60. HS200 Interface Timing Specification
ID Parameter Symbols Min Max Unit
Card Input Clock
SD1 Clock Frequency Period t
CLK
5.0 ns
SD2 Clock Low Time t
CL
0.46 × t
CLK
0.54 × t
CLK
ns
SD2 Clock High Time t
CH
0.46 × t
CLK
0.54 × t
CLK
ns
uSDHC Output/Card Inputs SD_CMD, SDx_DATAx in HS200 (Reference to CLK)
SD5
uSDHC Output Delay t
OD
–1.6 1 ns
uSDHC Input/Card Outputs SD_CMD, SDx_DATAx in HS200 (Reference to CLK)
1
1
HS200 is for 8 bits while SDR104 is for 4 bits.
SD8
Card Output Data Window t
ODW
0.5*t
CLK
—ns
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